Metal-oxide-semiconductor capacitor structure
AssigneeUnited Microelectronics Corp.
InventorsPin-Tseng Chen, Ling-Chun Chou, Kun-Hsien Lee
Life of this patent
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Abstract
The invention provides a metal oxide semiconductor (MOS) capacitor structure, which includes a counter-doping region in the channel region directly below the gate. Between the deep ion well and the counter-doping region is a semiconductor region. The doping concentration of the semiconductor region is lower than that of the deep ion well. The P-type well ion implantation processes in the active region of the device can be omitted, so the production cost is lower, and the dosage of the counter-doping region can be reduced, which improves the time-dependent dielectric collapse (TDDB) issue.
Claims20
A metal-oxide-semiconductor (MOS) capacitor structure, comprising:
- a substrate having a first conductivity type;
- a first trench isolation structure disposed in the substrate and surrounding an active area of the substrate;
- a source region disposed in the active area;
- a drain region disposed in the active area and spaced apart from the source region, wherein the source region and the drain region have a second conductivity type;
- a channel region disposed between the source region and the drain region;
- a counter doping region disposed in the channel region, wherein the counter doping region has the second conductivity type, wherein the counter doping region has a portion that overlaps with the source region and the drain region, and wherein a bottom of the source region and a bottom of the drain region are lower than a bottom of the portion of the counter doping region overlapping with the source region and the drain region;
- a deep ion well disposed in the substrate under the channel region, wherein the deep ion well has the second conductivity type;
- a first semiconductor region between the deep ion well and the counter doping region and directly under the counter doping region;
- a gate disposed over the channel region;
- and
- a gate dielectric layer disposed between the gate and the channel region;
- wherein a doping concentration of the first semiconductor region is lower than a doping concentration of the deep ion well.
A metal-oxide-semiconductor (MOS) capacitor structure, comprising:
- a substrate having a first conductivity type;
- a first trench isolation structure disposed in the substrate and surrounding an active area of the substrate;
- a source region disposed in the active area;
- a drain region disposed in the active area and spaced apart from the source region, wherein the source region and the drain region have a second conductivity type;
- a channel region disposed between the source region and the drain region;
- a counter doping region disposed in the channel region, wherein the counter doping region has the second conductivity type, wherein the counter doping region has a portion that overlaps with the source region and the drain region, and wherein a bottom of the source region and a bottom of the drain region are lower than a bottom of the portion of the counter doping region overlapping with the source region and the drain region;
- a deep ion well disposed in the substrate directly under the channel region, wherein the deep ion well has the second conductivity type;
- a first semiconductor region between the deep ion well and the counter doping region;
- a second semiconductor region disposed between the source region and the deep ion well and between the drain region and the deep ion well in the substrate, and wherein the second semiconductor region surrounds the first semiconductor region, wherein a doping concentration of the second semiconductor region is greater than a doping concentration of the first semiconductor region;
- a gate disposed over the channel region;
- and
- a gate dielectric layer disposed between the gate and the channel region;
- wherein the doping concentration of the first semiconductor region is lower than a doping concentration of the deep ion well.
Dependencies are inferred from the claim text.