Semiconductor device including dummy stacked structure and electronic system including the same

A semiconductor device comprising:

• a peripheral circuit structure including a cell region and an outside region;
• a cell structure on the cell region of the peripheral circuit structure;
• an outside structure on the outside region of the peripheral circuit structure;
• and
• an insulating layer on the peripheral circuit structure, wherein
• the cell structure includes
• a cell substrate,
• a lower electrode structure on the cell substrate,
• an upper electrode structure on the lower electrode structure,
• a channel structure penetrating the lower electrode structure and the upper electrode structure,
• an upper horizontal electrode on the channel structure, and
• an upper semiconductor pattern penetrating the upper horizontal electrode,
• the lower electrode structure includes a lower electrode and a lower mold insulating layer alternately stacked in the cell structure,
• the upper electrode structure includes an upper electrode and an upper mold insulating layer alternately stacked on the lower electrode structure,
• the upper semiconductor pattern is connected to the channel structure,
• the outside structure includes
• a lower dummy stacked structure,
• an upper dummy stacked structure,
• a through electrode penetrating the upper dummy stacked structure and the lower dummy stacked structure, and
• a plurality of dummy vertical structures surrounding the through electrode, and
• the lower dummy stacked structure is level with the lower electrode structure,
• the lower dummy stacked structure includes the lower mold insulating layer and a lower dummy pattern alternately stacked,
• the upper dummy stacked structure is level with the upper electrode structure,
• the upper dummy stacked structure includes the upper mold insulating layer and an upper dummy pattern alternately stacked,
• the through electrode is connected to the peripheral circuit structure,
• the plurality of dummy vertical structures penetrate a portion of the upper dummy stacked structure, in a plan view,
• the insulating layer is between the lower dummy stacked structure and the peripheral circuit structure,
• at least a portion of the insulating layer is between the plurality of dummy vertical structures and the peripheral circuit structure,
• wherein an upper surface of each of the plurality of dummy vertical structures has a rounded shape in a plan view.

An electronic system comprising:

• a main substrate;
• a semiconductor device on the main substrate;
• and
• a controller electrically connected to the semiconductor device on the main substrate, wherein
• the semiconductor device includes
• a peripheral circuit structure including a cell region and an outside region,
• a cell structure on the cell region of the peripheral circuit structure,
• an outside structure on the outside region of the peripheral circuit structure, and
• an insulating layer on the peripheral circuit structure,
• the cell structure includes
• an electrode structure including electrodes alternately arranged on the cell region,
• a channel structure penetrating the electrode structure,
• a conductive pattern connected to the channel structure,
• an upper horizontal electrode on the electrode structure and the conductive pattern, and
• an upper semiconductor pattern penetrating the upper horizontal electrode,
• the upper semiconductor pattern is connected to the conductive pattern,
• the outside structure includes
• a dummy stacked structure,
• a through electrode penetrating the dummy stacked structure and connected to the peripheral circuit structure, and
• a plurality of dummy vertical structures adjacent to the through electrode and penetrating at least a portion of the dummy stacked structure,
• the dummy stacked structure includes an upper dummy stacked structure on a lower dummy stacked structure,
• the upper dummy stacked structure includes upper dummy patterns stacked on the lower dummy stacked structure,
• the lower dummy stacked structure includes lower dummy patterns stacked on the outside region,
• the insulating layer is between the dummy stacked structure and the peripheral circuit structure, and
• at least a portion of the insulating layer is between the plurality of dummy vertical structures and the peripheral circuit structure,
• wherein an upper surface of each of the plurality of dummy vertical structures has a rounded shape in a plan view.