US 12,757,400 B2 · 3D memory with reduced leakage current

Abstract

A memory device includes a stacked structure, a first conductive type doping layer, a second conductive type doping layer, a first conductive plug and a second conductive plug. The stacked structure is located above the substrate, and includes a plurality of conductive layers and a plurality of insulating layers alternately stacked. A projection area of the first conductive type doping layer is larger than a projection area of the stacked structure. The second conductive type doping layer surrounds the first conductive type doping layer and forms a hetero-junction with the first conductive type doping layer. The first conductive plug is electrically connected to the first conductive type doping layer. The second conductive plug is electrically connected to the second conductive type doping layer. The memory device may be a 3D AND flash memory.

Claims18

Dependent claims

A memory device, comprising:

a stacked structure, located above a substrate, wherein the stacked structure comprises a plurality of conductive layers and a plurality of insulating layers alternately stacked;
a first conductive type doping layer, located between the stacked structure and the substrate, a projection area of the first conductive type doping layer being larger than a projection area of the stacked structure;
a second conductive type doping layer, surrounding the first conductive type doping layer and forming a hetero-junction with the first conductive type doping layer;
a first conductive plug, electrically connected to the first conductive type doping layer;
and
a second conductive plug, electrically connected to the second conductive type doping layer.

3 more elements

A memory device, comprising:

a first conductive type doping layer, located above a substrate and comprising a first portion and a second portion separated from each other;
a second conductive type doping layer, located above the substrate, surrounding the first portion and the second portion, wherein the second conductive type doping layer comprises:
a middle portion, located between the first portion and the second portion of the first conductive type doping layer;
a peripheral portion, surrounding the first portion and the second portion of the first conductive type doping layer;
a stacked structure, located above the first portion of the first conductive type doping layer, above the middle portion of the second conductive type doping layer, and above the second portion of the first conductive type doping layer, wherein the stacked structure comprises a plurality of conductive layers and a plurality of insulating layers alternately stacked;
and
a pair of middle separation walls, extending through the stacked structure,
wherein a side of a first middle separation wall of the pair of middle separation walls is located adjacent to the first portion of the first conductive type doping layer, a side of a second middle separation wall of the pair of middle separation walls is located adjacent to the second portion of the first conductive type doping layer, and another side of the first middle separation wall and another side of the second middle separation wall are located adjacent to the middle portion of the second conductive type doping layer.

5 more elements

Dependencies are inferred from the claim text.

3D memory with reduced leakage current

Life of this patent

3D memory with reduced leakage current

Life of this patent

Abstract

Claims18