Semiconductor memory device and method of manufacturing the semiconductor memory device

#The present application claims priority under 35 U.S.C. § 119(a) to Korean patent application number 10-2022-0051738, filed on Apr. 27, 2022, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

#Various embodiments of the present disclosure generally relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device, and more particularly to a three-dimensional (3D) semiconductor memory device and a method of manufacturing the 3D semiconductor memory device.

#A semiconductor memory device includes memory cells capable of storing data. A three-dimensional (3D) semiconductor memory device may include a 3D memory cell array.

#FIG. 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure.

#FIGS. 2A and 2B are views schematically illustrating the arrangement of a peripheral circuit structure, a memory cell array, a plurality of bit lines, and a horizontal doped semiconductor pattern according to embodiments of the present disclosure.

#FIGS. 3A and 3B are circuit diagrams illustrating a memory cell array according to embodiments of the present disclosure.

#Specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. Embodiments according to the concept of the present disclosure can be implemented in various forms, and should not be construed as being limited to the specific embodiments set forth herein.

#Hereinafter, the terms ‘first’ and ‘second’ are used to distinguish one component from another component and are not meant to imply a specific number or order of components. The terms may be used to describe various components, but the components are not limited by the terms. It will be understood that when an element or layer etc., is referred to as being “on,” “connected to” or “coupled to” another element or layer etc., it can be directly on, connected or coupled to the other element or layer etc., or intervening elements or layers etc., may be present. In contrast, when an element or layer etc., is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer etc., there are no intervening elements or layers etc., present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

#Various embodiments of the present disclosure are directed to a semiconductor memory device that is capable of securing an alignment margin and improving operational reliability, and a method of manufacturing the semiconductor memory device.