Semiconductor devices having landing pad structures

A semiconductor device, comprising:

• a substrate including an active region;
• a cell gate structure disposed in the substrate, crossing the active region, and extending in a first horizontal direction;
• bitline structures crossing the cell gate structure and extending in a second horizontal direction intersecting the first horizontal direction;
• a contact plug disposed between the bitline structures;
• a landing pad structure disposed on the contact plug and including a lower landing pad and an upper landing pad on the lower landing pad, the upper landing pad including a cavity;
• an insulating pattern structure in contact with one of the bitline structures and in contact with the landing pad structure;
• and
• a capacitor structure including a lower electrode disposed on the landing pad structure and electrically connected to the landing pad structure, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer,
• wherein a portion of the lower electrode extends into the cavity of the upper landing pad.

A semiconductor device, comprising:

• a substrate including a cell region and a peripheral circuit region;
• a first active region disposed on the substrate in the cell region;
• a second active region disposed on the substrate in the peripheral circuit region;
• a cell gate structure disposed in the substrate in the cell region, crossing the first active region, and extending in a first horizontal direction;
• bitline structures crossing the cell gate structure and extending in a second horizontal direction intersecting the first horizontal direction;
• a contact plug disposed between the bitline structures;
• a landing pad structure disposed on the contact plug and including a lower landing pad and an upper landing pad on the lower landing pad, the upper landing pad including a cavity;
• a conductive pattern disposed in the cavity of the upper landing pad;
• a peripheral gate structure disposed on the substrate in the peripheral circuit region;
• a peripheral contact plug adjacent to the peripheral gate structure and connected to the second active region;
• and
• a peripheral wiring layer on the peripheral contact plug.