US 12,757,379 B2 · Semiconductor memory device with vertical channel transistors including multiple word lines

Abstract

There is provided a semiconductor memory device having improved integration and electrical characteristics. The semiconductor memory device includes a bit line extending in a first direction on a substrate, a first channel pattern disposed on the bit line, a second channel pattern disposed on the bit line and spaced apart from the first channel pattern in the first direction, a first word line disposed between the first channel pattern and the second channel pattern extends in a second direction, a second word line disposed between the first channel pattern and the second channel pattern, extends in the second direction, and is spaced apart from the first word line in the first direction, and a first capacitor and a second capacitor disposed on and connected to the first channel pattern and the second channel pattern, respectively, wherein each of the first channel pattern and the second channel pattern includes a first metal oxide pattern including indium (In), gallium (Ga) and tin (Sn), and a position of a peak of tin is different from a position of a peak of gallium in a spatial composition distribution of the first metal oxide pattern.

Claims20

Dependent claims

A semiconductor memory device comprising:

a bit line extending in a first direction on a substrate;
a first channel pattern disposed on the bit line;
a second channel pattern disposed on the bit line and spaced apart from the first channel pattern in the first direction;
a first word line disposed between the first channel pattern and the second channel pattern and extending in a second direction;
a second word line disposed between the first channel pattern and the second channel pattern, extending in the second direction and is spaced apart from the first word line in the first direction;
and
a first capacitor and a second capacitor disposed on and connected to the first channel pattern and the second channel pattern, respectively,
wherein each of the first channel pattern and the second channel pattern includes a first metal oxide pattern including indium (In), gallium (Ga), and tin (Sn), and
a position of a peak of tin is different from a position of a peak of gallium in a spatial composition distribution of the first metal oxide pattern.

6 more elements

A semiconductor memory device comprising:

a peri-gate structure on a substrate;
a bit line disposed on the peri-gate structure and extending in a first direction;
a channel structure disposed on the bit line, the channel structure including a horizontal portion, and a first vertical portion and a second vertical portion protruding from the horizontal portion;
a first word line disposed on the channel structure and extending in a second direction;
a second word line disposed on the channel structure, extending in the second direction, and spaced apart from the first word line in the first direction;
a gate separation pattern disposed in the horizontal portion of the channel structure and separating the first word line and the second word line;
a plurality of landing pads disposed on and connected to the channel structure;
and
a plurality of data storage patterns disposed on the landing pads,
wherein the channel structure includes a first metal oxide pattern including indium (In), gallium (Ga), and tin (Sn), and
wherein a ratio of tin in the first metal oxide pattern ranges between 15 at. % and 30 at. %.

8 more elements

Dependencies are inferred from the claim text.

Semiconductor memory device with vertical channel transistors including multiple word lines

Life of this patent

Semiconductor memory device with vertical channel transistors including multiple word lines

Life of this patent

Abstract

Claims20