Semiconductor memory device

A semiconductor memory device comprising a memory cell string comprising a plurality of memory cells arranged in a line in a vertical direction,

• wherein each of the plurality of memory cells comprises:
• a word line extending in a lateral direction;
• a sensing line apart from the word line, the sensing line overlapping the word line in the vertical direction and extending in the lateral direction;
• a vertical semiconductor structure passing through the word line and the sensing line in the vertical direction, the vertical semiconductor structure having a vertical channel region facing the word line in the lateral direction;
• and
• a gate dielectric film between the vertical channel region and the word line,
• wherein, in each of the plurality of memory cells, the vertical semiconductor structure comprises a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type, which are sequentially provided in the vertical direction,
• wherein the vertical channel region comprises the first lightly doped film or the second lightly doped film in each of the plurality of memory cells, and
• wherein the sensing line is in contact with the first heavily doped film of the vertical semiconductor structure in each of the plurality of memory cells.

A semiconductor memory device comprising a memory cell array comprising a plurality of memory cells three-dimensionally and repeatedly arranged on a substrate in a first lateral direction, a second lateral direction, and a vertical direction, wherein the first lateral direction crosses the second lateral direction, and the vertical direction is perpendicular to each of the first lateral direction and the second lateral direction,

• wherein the memory cell array comprises:
• a plurality of sensing lines and a plurality of word lines alternately arranged, one-by-one, in the vertical direction, the plurality of sensing lines and the plurality of word lines being apart from each other in the vertical direction;
• a plurality of insulating films respectively between the plurality of sensing lines and the plurality of word lines;
• a stack structure passing through the plurality of sensing lines, the plurality of word lines, and the plurality of insulating films in the vertical direction, the stack structure comprising a plurality of vertical semiconductor structures overlapping each other in the vertical direction, each of the plurality of vertical semiconductor structures having a vertical channel region;
• an insulating pillar passing through the plurality of vertical semiconductor structures in the vertical direction;
• a plurality of gate dielectric films between respective vertical channel regions of the plurality of vertical semiconductor structures and the plurality of word lines;
• and
• a plurality of bit lines passing through the plurality of insulating films,
• wherein, from among the plurality of memory cells, memory cells arranged in a line in the vertical direction share a selected one of the plurality of bit lines,
• wherein each of the plurality of vertical semiconductor structures comprises a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type, which are sequentially provided in the vertical direction, and
• wherein the vertical channel region of each of the plurality of vertical semiconductor structures comprises the first lightly doped film or the second lightly doped film.