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US 12,756,391 B2Granted
RF switch stack with charge control elements
AssigneepSemi Corporation
InventorsEric S. Shapiro, Simon Edward Willard
Life of this patent
Estimating the term…
Abstract
Methods and devices to address the undesired DC voltage distribution across switch stacks in OFF state are disclosed. The disclosed devices include charge control elements that sample the RF signal to generate superimposed voltages at specific points of the switch stack biasing circuit. The provided voltages help reducing the drooping voltages on drain/source/body terminals of the transistors within the stack by supplying the current drawn by drain/source terminals of the stacked transistors and/or by sinking the body leakage current exiting the body terminals of such transistors. Methods and techniques teaching how to provide proper tapping points in the biasing circuit to sample the RF signal are also disclosed.
Claims20
A FET switch stack comprising:
- a plurality of field effect transistors (FETs) connected in series;
- a first drain-source resistor network including a serial connection of at least two first drain-source resistors connected to each other at a first tapping point, the serial connection of the at least two first drain-source resistors having a first terminal and a second terminal;
- and
- a second drain-source resistor network including a serial connection of at least two second drain-source resistors connected to each other at a second tapping point, the serial connection of the at least two second drain-source resistors having a third terminal and a fourth terminal;
- wherein:
- the plurality of FETs is connected at one end to a first radio frequency (RF) terminal;
- the plurality of FETs comprises a first FET and a second FET, a source terminal of the first FET being connected to a drain terminal of the second FET;
- the third terminal is coupled to a drain terminal of the second FET and the fourth terminal is coupled to a source terminal of the second FET;
- the first terminal is coupled to a drain terminal of the first FET and the second terminal is coupled to a source terminal of the first FET, and
- the FET switch stack is configured such that, during operation with an applied RF signal, the first tapping point and a gate terminal of the first FET are electrically at different radio frequency (RF) voltage potentials.
7 more elements
A FET switch stack comprising:
- a plurality of field effect transistors (FETs) connected in series;
- and
- a first drain-source resistor network including a serial connection of at least two first drain-source resistors connected to each other at a first tapping point;
- wherein:
- the plurality of FETs is connected at one end to a first radio frequency (RF) terminal;
- the plurality of FETs comprises a first FET and a second FET, a source terminal of the first FET being connected to a drain terminal of the second FET;
- a first terminal is coupled to a drain terminal of the first FET and a second terminal is coupled to a source terminal of the first FET;
- and
- the FET switch stack further comprises a second drain-source resistor network including a serial connection of at least two second drain-source resistors connected to each other at a second tapping point, the serial connection of the at least two second drain-source resistors having a third terminal and a fourth terminal, and wherein the third terminal is coupled to a drain terminal of the second FET and the fourth terminal is coupled to a source terminal of the second FET.
6 more elements
A FET switch stack comprising:
- a plurality of field effect transistors (FETs) connected in series;
- a first drain-source resistor network including a serial connection of at least two first drain-source resistors connected to each other at a first tapping point, the serial connection of the at least two first drain-source resistors having a first terminal and a second terminal;
- a second drain-source resistor network including a serial connection of at least two second drain-source resistors connected to each other at a second tapping point, the serial connection of the at least two second drain-source resistors having a third terminal and a fourth terminal, and wherein the third terminal is coupled to a drain terminal of the second FET and the fourth terminal is coupled to a source terminal of the second FET;
- a drain-source charge control element connected to the first tapping point and the second tapping point, and
- the drain-source charge control element comprising a first diode connected between the first tapping point and a first charge control resistor and a second diode connected between the second tapping point and a second charge control resistor;
- wherein:
- the plurality of FETs is connected at one end to a first radio frequency (RF) terminal;
- the plurality of FETs comprises a first FET and a second FET, a source terminal of the first FET being connected to a drain terminal of the second FET;
- the first terminal is coupled to a drain terminal of the first FET and the second terminal is coupled to a source terminal of the first FET.
6 more elements
Dependencies are inferred from the claim text.