Low hold multi-bit flip-flop
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsSeid Hadi Rasouli, Jerry Chang Jui Kao, Xiangdong Chen, Tzu-Ying Lin, Yung-Chen Chien, Shao-Lun Chien
Life of this patent
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Abstract
Circuits, systems, and methods are described herein for increasing a hold time of a master-slave flip-flop. A flip-flop includes circuitry configured to receive a scan input signal and generate a delayed scan input signal; a master latch configured to receive a data signal and the delayed scan input signal; and a slave latch coupled to the master latch, the master latch selectively providing one of the data signal or the delayed scan input signal to the slave latch based on a scan enable signal received by the master latch.
Claims20
A flip-flop comprising:
- first circuitry configured to receive a scan input signal and a scan enable signal and to generate a delayed scan input signal;
- a latch configured to output a data signal or the delayed scan input signal based on the scan enable signal;
- and
- second circuitry configured to provide a clock signal to the latch and to receive an inverted version of the scan enable signal.
A method comprising:
- generating, by first circuitry, a delayed scan input signal based on a scan input signal and a scan enable signal;
- outputting, by a latch, a data signal or the delayed scan input signal based on the scan enable signal;
- providing, by second circuitry, a clock signal to the latch;
- and
- receiving, by the second circuitry, an inverted version of the scan enable signal.
A flip-flop comprising:
- first circuitry configured to generate a delayed version of a first signal based on the first signal and a second signal;
- a latch coupled to the first circuitry and configured to selectively output the delayed version of the first signal based on the second signal;
- and
- second circuitry configured to provide a clock signal to the latch and to receive an inverted version of the second signal.
Dependencies are inferred from the claim text.