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US 12,754,878 B2Granted
Adiabatic circuits for cold scalable electronics
AssigneeZettaflops LLC
InventorErik DeBenedictis
Life of this patent
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Abstract
A system and method comprising a cryogenic adiabatic circuit in a cryogenic environment and a clock generator at a higher temperature, the circuit's clock lines can be connected across the temperature gradient to the clock generator, where the clock generator runs below the frequency that would yield power dissipation equal to the static dissipation of a functionally equivalent CMOS circuit at room temperature, resulting in lower power for the function than possible at room temperature irrespective of the speed of operation.
Claims20
A system comprising:
- a second stage comprising a Josephson junction circuit configured to contain information;
- a first stage comprising a transistor circuit comprising logic and cells that store the information, wherein the information can be moved from the first stage to the second stage and the information can be moved from the second stage to the first stage;
- and
- at least one transistor, wherein a leakage current of the at least one transistor is rebalanced for cryogenic operation.
1 more element
A system comprising:
- a second stage comprising a Josephson junction circuit comprising a single-flux quantum (SFQ) circuit configured to contain information;
- a qubit-containing payload, wherein the information is transferred to the payload;
- a first stage comprising a transistor circuit comprising a tapped adiabatic SRAM, wherein information in the SRAM is transferred to the payload via taps wherein the transistor circuit is configured to comprise logic and cells that store the information, wherein the information can be moved from the first stage to the second stage and the information can be moved from the second stage to the first stage.
A system comprising:
- a second stage comprising a Josephson junction circuit configured to contain information;
- a first stage comprising a transistor circuit comprising logic and cells that store the information wherein the information can be moved from the first stage to the second stage and the information can be moved from the second stage to the first stage;
- and
- a semiconductor FET that either passes or blocks an SFQ pulse based on the information.
1 more element
Dependencies are inferred from the claim text.