Semiconductor device, storage system and operation method
AssigneeWinbond Electronics Corp.
InventorTakehiro Kaminaga
Life of this patent
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Abstract
Provided is a semiconductor device that combines a NOR flash memory and a NAND flash memory. A stacked flash memory includes a NOR flash memory, a NAND flash memory, a controller, and an external bus that can input/output data in synchronization with a serial clock signal. When receiving a read command according to specifications of the NOR flash memory from the external bus, the controller responds the read command to cause a portion of specific data read from the NOR flash memory to be serially output, and then cause a remaining portion of the specific data read from the NAND flash memory to be serially output. In this way, data is read from the expanded NAND flash memory in the same manner as accessing the NOR flash memory.
Claims15
A semiconductor device, comprising a NOR flash memory and a NAND flash memory, wherein the semiconductor device comprises:
- an input/output component capable of inputting/outputting data via an input/output bus in synchronization with a serial clock signal;
- and
- a controller component controlling operations of the NOR flash memory and the NAND flash memory,
- wherein in response to a read instruction received from the input/output component, the controller component causes a portion of specific data read from the NOR flash memory to be serially output from the input/output component, and then causes a remaining portion of the specific data read from the NAND flash memory to be serially output from the input/output component.
An operation method, comprising a method of operating a semiconductor device comprising a NOR flash memory and a NAND flash memory, wherein
- in response to a read instruction received from an input/output component, a controller component controlling operations of the NOR flash memory and the NAND flash memory causes a portion of specific data read from the NOR flash memory to be serially output, and then causes a remaining portion of the specific data read from the NAND flash memory to be serially output.
Dependencies are inferred from the claim text.