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US 12,750,055 B2Granted
Device and methods for switch control
AssigneeMicrochip Technology Incorporated
InventorsAndreas Reiter, Yong Yuenyongsgool, Stephen Bowling, Tim Phoenix, Alex Dumais, Justin Oshea
Life of this patent
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Abstract
A device includes a PWM circuit to generate a complementary PWM signal comprised of a positive polarity PWM signal and a negative polarity PWM signal. The positive polarity signal may drive a high-side switch. A trigger multiplexer may take as input the negative polarity PWM signal and may force an output based on a predetermined condition, the predetermined condition including but not limited to the maximum on-time of a low-side switch. The output of the trigger multiplexer may drive a low-side switch. The high-side switch and the low-side switch may drive a load.
Claims20
A device for switch control comprising:
- a pulse-width modulator (PWM) circuit, the PWM modulator circuit to receive an input signal and to output a positive polarity PWM signal and a negative polarity PWM signal, the negative polarity PWM signal the complement of the positive polarity signal;
- an AND gate with a first input coupled to a trigger event signal and a second input coupled to a low-side active control signal;
- a trigger multiplexer with a first input coupled to the negative polarity PWM signal, a second input coupled to a logic low level, and a select input coupled to the output of the AND gate, the output of the trigger multiplexer coupled to a switch, the output of the switch coupled to a low-side drive signal, the low-side drive signal forced to a logic low level based solely on the output of the AND gate;
- a low-side switch with a gate node coupled to the low-side drive signal, a source node coupled to a fixed voltage, and a drain node coupled to a load, and
- a high-side switch with a gate node coupled to the positive polarity PWM signal, a source node coupled to a supply voltage, and a drain node coupled to the load.
2 more elements
A system for switch control comprising:
- a pulse-width modulator (PWM) circuit, the PWM circuit to output a positive polarity PWM signal and a negative polarity PWM signal, the negative polarity PWM signal the complement of the positive polarity signal;
- a PWM conditioning circuit coupled to the outputs of the PWM circuit, the PWM conditioning circuit to modify the positive polarity PWM signal, and to modify the negative polarity PWM signal, the PWM conditioning circuit to output a high-side drive signal and a low-side drive signal, wherein the PWM conditioning circuit forces the low-side drive signal to an inactive state based on an output of an AND gate and based on a switch coupled to an output of the AND gate, the AND gate with a first input coupled to an output of a central processing unit (CPU) and a second input coupled to a low-side active control signal, the PWM conditioning circuit further comprising:
- a high-side dead time generator coupled to the positive polarity PWM signal, a low-side dead-time generator coupled to the negative polarity PWM signal, and a trigger multiplexer with a first input coupled to the output of the low-side dead-time generator, the trigger multiplexer output to force the low-side switch to an inactive state based solely an output of the AND gate;
- a first switch coupled to an output of the high-side dead-time generator, the first switch to force the high-side switch to an active state, and
- a second switch coupled to the output of the low-side dead-time generator, the second switch to force the low-side switch to an active state;
- a low-side switch with a gate node directly coupled to the low-side drive signal, a source node coupled to a fixed voltage, and a drain node coupled to a load, and
- a high-side switch with a gate node coupled to the high-side drive signal, a source node coupled to a supply voltage, and a drain node coupled to the load.
4 more elements
A method for switch control comprising:
- generating a positive polarity PWM signal and a negative polarity PWM signal, the negative polarity PWM signal the complement of the positive polarity PWM signal;
- modifying the positive polarity PWM signal to generate a high-side drive signal;
- forcing the negative polarity PWM signal to an inactive state based solely on an output of an AND gate to generate a low-side drive signal, the AND gate comprising a first input coupled to a trigger event signal and a second input coupled to a low-side active control signal;
- forcing the low-side drive signal high by a switch;
- driving a low-side switch with the low-side drive signal, and
- driving a high-side switch with the high-side drive signal.
3 more elements
Dependencies are inferred from the claim text.