Systems and methods for adaptive gate voltage generation of pad-connected devices

A system comprising:

• a first, second and third PMOS transistor serially coupled between a first high voltage power supply and a pad, a gate of the first PMOS transistor coupled to a first signal from an internal circuit, the first signal configured to switch between a first voltage and the first high voltage power supply, the first voltage being lower than the first high voltage power supply, a gate of the second PMOS transistor being applied the first voltage, and a gate and drain of the third PMOS transistor connected to an adaptive control node and the pad, respectively;
• and
• a first, second and third NMOS transistor serially coupled between the pad and a ground, a gate of the first NMOS transistor coupled to a second signal from the internal circuit, the second signal configured to switch between a second voltage and the ground, the second voltage being higher than the ground but lower than the first voltage, a gate of the second NMOS transistor being applied the second voltage, and a gate and drain of the third NMOS transistor connected to the adaptive control node and the pad, respectively,
• wherein the adaptive control node is configured to switch between the first and second voltage, and
• wherein the adaptive control node is selectively coupled to a transmit logic circuit or a receive logic circuit in response to a state of an output enable signal.