Multi-level di/di control of a power semiconductor device

A control circuit for di/dt control of a power semiconductor device comprising:

• a power semiconductor die forming a power switch and comprising an input pad, an output pad, and a control pad;
• a collector power terminal coupled to the input pad of the power switch;
• an auxiliary gate terminal coupled to the control pad of the power switch;
• an emitter power terminal;
• two or more inductance and resistance pairs, wherein each inductance and resistance pair comprises a common stray inductance and a resistance that are arranged in series between the output pad of the power switch and the emitter power terminal;
• a plurality of auxiliary emitter terminals, wherein the auxiliary emitter terminals are coupled to both sides of the inductance and resistance pairs so that one auxiliary emitter terminal is coupled to one side of one inductance and resistance pair,
• wherein the control circuit is configured to be coupled to a plurality of inductance and resistance pairs of the power semiconductor device,
• wherein the control circuit is configured to form a gate drive current return loop through an inductance and resistance pair, and
• wherein the control circuit is configured to select the inductance and resistance pair;
• a plurality of electronic switches, wherein each electronic switch of the plurality of electronic switches is configured to be coupled to one side of one inductance and resistance pair;
• an input configured to receive a di/dt selection input signal;
• a demultiplexer circuit configured to receive the di/dt selection input signal via the input and coupled to the plurality of electronics switches;
• and
• one or more oscillation damp resistors coupled between the electronics switches and a gate drive power supply ground.

An electronic device comprising:

• a power semiconductor device comprising:
• a power semiconductor die forming a power switch and comprising an input pad, an output pad, and a control pad,
• a collector power terminal coupled to the input pad of the power switch,
• an auxiliary gate terminal coupled to the control pad of the power switch,
• an emitter power terminal,
• two or more inductance and resistance pairs,
• wherein each inductance and resistance pair comprises a common stray inductance and a resistance that are arranged in series between the output pad of the power switch and the emitter power terminal,
• a plurality of auxiliary emitter terminals,
• wherein the auxiliary emitter terminals are coupled to both sides of the inductance and resistance pairs so that one auxiliary emitter terminal is coupled to one side of one inductance and resistance pair;
• and
• a control circuit comprising a plurality of electronic switches, wherein each electronic switch of the plurality of electronic switches is configured to be coupled to one side of one inductance and resistance pair,
• wherein the control circuit is configured to be coupled to a plurality of inductance and resistance pairs of the power semiconductor device,
• wherein the control circuit is configured to form a gate drive current return loop through an inductance and resistance pair, and
• wherein the control circuit is configured to select the inductance and resistance pair.