Current sensing implementation for common-drain, back-to-back power switches in vertical FET technology

A device comprising:

• a power field effect transistor (FET) device instantiated on a first die, the power FET device comprising:
• a first power FET;
• a second power FET disposed back-to-back with respect to the first power FET, wherein the first power FET and the second power FET are connected to a common drain node within the first die;
• a first replica FET coupled to the common drain node and configured to provide a sense current representative of a load current flowing through the power FET device;
• and
• a second replica FET coupled to the common drain node and configured to provide a sense voltage representative of a voltage of the common drain node;
• and
• a current sense circuit coupled to the first replica FET and the second replica FET and configured to:
• use the sense voltage from the second replica FET to draw the sense current through the first replica FET;
• detect the voltage of the common drain node provided by the second replica FET;
• and
• generate a second voltage to be applied on a source terminal of the first replica FET to match a drain-to-source voltage drop across the first power FET to generate the sense current.

A power field effect transistor (FET) device comprising:

• a first power FET and a second power FET arranged in series and electrically coupled through a common drain node, wherein the first power FET and the second power FET are configured to deliver an output current to a load responsive to a first gate drive signal coupled to the first power FET through a first gate terminal of the power FET device, and a second gate drive signal coupled to the second power FET through a second gate terminal of the power FET device;
• a first replica FET to provide a sense current that is proportional to the output current;
• and
• a second replica FET to provide a sense voltage corresponding to a voltage of the common drain node, wherein a drain of the first replica FET and the second replica FET are coupled to the common drain node, wherein the power FET device is instantiated on a first die disposed within a semiconductor package as a System-in-Package (SiP), and wherein the semiconductor package further comprises an integrated circuit (IC) controller instantiated on a second die.