Flip-flop with a high-speed architecture

A method performed by a flip-flop, the method comprising:

• propagating, based on a first clock signal, a first signal from a first input of the flip-flop to an output of the flip-flop along a first path of the flip-flop, the first path having a pulsed-latch topology between the first input of the flip-flop and the output of the flip-flop, the pulsed-latch topology comprising a single latch between the first input and the output, the single latch comprising a first pass-gate circuit, the first clock signal having a first duty cycle;
• and
• propagating, based on a second clock signal, a second signal from a second input of the flip-flop to the output of the flip-flop along a second path of the flip-flop, the second path having a master-slave topology between the second input of the flip-flop and the output of the flip-flop, the master-slave topology comprising two latches, the two latches comprising pass-gate circuits that are distinct from the first pass-gate circuit of the pulsed-latch topology, the second clock signal having a second duty cycle that is greater than the first duty cycle,
• the propagating of the first signal and the propagating of the second signal comprising propagating the first signal and the second signal through a keeper circuit of the flip-flop, the keeper circuit coupled between a shared node of the flip-flop and the output of the flip-flop, the keeper circuit existing within the first and second paths, the keeper circuit representing a portion of the pulsed-latch topology and representing a portion of the master-slave topology.