Toggle flip-flop and counter including the same
AssigneesSamsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
InventorsJaeha Lee, Bai-Sun Kong, Bomin Joo
Life of this patent
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Abstract
A flip-flop configured to generate an output toggling according to an input clock includes an inverter configured to generate the output by inverting a first data signal, a first circuit configured to generate a second data signal based on an input clock and a latch signal, a second circuit configured to generate the latch signal based on the input clock and the second data signal, and a third circuit configured to generate the first data signal using the input clock, the second data signal, and the latch signal, wherein the third circuit is further configured to pull down the first data signal, independently of the second data signal, using the input clock and the latch signal.
Claims20
A flip-flop configured to generate an output toggling according to an input clock, the flip-flop comprising:
- an inverter configured to generate the output by inverting a first data signal;
- a first circuit configured to generate a second data signal based on the input clock, the first data signal, and a latch signal;
- a second circuit configured to generate the latch signal based on the input clock and the second data signal;
- and
- a third circuit configured to generate the first data signal using the input clock, the second data signal, and the latch signal,
- wherein the third circuit is further configured to pull down the first data signal, independently of the second data signal, using the input clock and the latch signal.
A flip-flop configured to generate an output toggling according to an input clock, the flip-flop comprising:
- an inverter configured to generate the output by inverting a first data signal;
- a first circuit configured to generate a second data signal based on the input clock, the first data signal, and a latch signal;
- a second circuit configured to generate the latch signal based on the input clock and the second data signal;
- and
- a third circuit configured to generate the first data signal based on the input clock, the second data signal, and the latch signal,
- wherein the third circuit includes a first n-channel field effect transistor (NFET) and a second NFET connected between a first output node, at which the first data signal is generated, and a first power node, to which a negative supply voltage is applied, the first NFET and the second NFET respectively receiving the input clock and the latch signal.
A method of generating an output toggling according to an input clock, the method comprising:
- generating the output by inverting a first data signal;
- generating a second data signal by inverting the first data signal when the input clock is logic low and by inverting a latch signal when the input clock is logic high;
- generating the latch signal as logic high when the input clock is logic low and generating the latch signal by inverting the second data signal when the input clock is logic high;
- and
- holding the first data signal when the input clock is logic low and generating the first data signal by inverting the latch signal when the input clock is logic high.
Dependencies are inferred from the claim text.