Clock transmission circuit and semiconductor device including the same

A semiconductor device comprising:

• a first inverter configured to receive an input clock signal through a clock input terminal, invert the input clock signal to generate an inverted clock signal, and output the inverted clock signal to a clock output terminal, the input clock signal being input through a first interface;
• a feedback impedance circuit connected in parallel with the first inverter between the clock output terminal and the clock input terminal;
• an inverter chain unit having a smaller size than the first inverter to reduce a swing level of an output clock signal, including an odd number of second inverters connected in a chain form, connected to the clock output terminal, and configured to perform a de-emphasis operation using a delay of the odd number of second inverters to reduce a rising time and a falling time of the output clock signal while inverting the inverted clock signal to generate the output clock signal and output the output clock signal to the clock output terminal;
• and
• an output circuit configured to output an internal signal to a second interface in response to the output clock signal on the clock output terminal.

A clock transmission circuit comprising:

• a first node and a second node with a set physical distance therebetween;
• and
• a transmission unit including first driving units and second driving units that are alternatively connected to each other in a chain form between the first node and the second node, and configured to transmit a clock signal through the first driving units and the second driving units,
• wherein each of the first driving units comprises:
• a first inverter configured to invert a first input signal received through a first input terminal to generate an inverted first input signal, and output the inverted first input signal to a first output terminal;
• a feedback impedance circuit connected in parallel with the first inverter between the first output terminal and the first input terminal;
• and
• an inverter chain unit having a smaller size than the first inverter to reduce a swing level of a first output signal, including an odd number of second inverters connected in a chain form, connected to the first output terminal, and configured to perform a de-emphasis operation using a delay of the odd number of second inverters to reduce a rising time and falling time of the first output signal while inverting the inverted first input signal to generate the first output signal and output the first output signal to the first output terminal,
• wherein each of the second driving units comprises:
• a third inverter configured to invert a second input signal received through a second input terminal to generate an inverted first input signal and output the inverted second input signal to a second output terminal.

A semiconductor device comprising:

• a reception unit configured to receive a clock signal input through a first interface;
• a transfer unit configured to transfer an internal signal to a second interface in response to the clock signal;
• and
• a transmission unit including first driving units and second driving units that are alternately connected to each other in a chain form, and configured to transmit the clock signal received from the reception unit to the transfer unit,
• wherein each of the first driving units comprises:
• a first inverter configured to invert a first input signal received through a first input terminal to generate an inverted first input signal, and output the inverted first input signal to a first output terminal;
• a feedback impedance circuit connected in parallel with the first inverter between the first output terminal and the first input terminal;
• and
• an inverter chain unit having a smaller size than the first inverter to reduce a swing level of a first output signal, including an odd number of second inverters connected in a chain form, connected to the first output terminal, and configured to perform a de-emphasis operation using a delay of the odd number of second inverters to reduce a rising time and falling time of the first output signal while inverting the inverted first input signal to generate the first output signal and output the first output signal to the first output terminal,
• wherein each of the second driving units comprises:
• a third inverter configured to invert a second input signal received through a second input terminal to generate an inverted first input signal and output the inverted second input signal to a second output terminal.