Time to digital converter (TDC) circuit with self-adaptive time granularity and related methods

A phase-locked loop (PLL) circuit comprising:

• a phase and frequency detection (PFD) circuit configured to generate a start signal and a stop signal separated by a time period based on a difference between a generated signal and a reference signal;
• an adaptive time-to-digital converter (TDC) circuit, comprising:
• a first series of serially coupled first delay circuits, the first series comprising a first series input and a first series output, wherein each of the first delay circuits is configured to provide a first signal delay from a first delay input to a first delay output;
• a second series of serially coupled second delay circuits, the second series comprising a second series input and a second series output, wherein each of the second delay circuits is configured to provide a second signal delay from a second delay input to a second delay output;
• a plurality of first storage circuits, each first storage circuit comprising:
• a first clock input coupled to the second series input;
• a first data input coupled to the first delay output of a corresponding one of the first delay circuits in the first series;
• and
• a first data output coupled to a first decoder;
• and
• a plurality of second storage circuits, each second storage circuit comprising:
• a second clock input coupled to the second delay output of a corresponding one of the second delay circuits in the second series;
• a second data input coupled to the first delay output of a corresponding one of the first delay circuits in the first series;
• and
• a second data output coupled to a second decoder;
• wherein:
• the first decoder is configured to generate a first indication of a first time period from a first start signal on the first series input to a first stop signal on the second series input;
• and
• the second decoder is configured to generate a second indication of a second time period from a second start signal on the first series input to a second stop signal on the second series input;
• a loop filter circuit coupled to the adaptive TDC circuit;
• and
• a digitally-controlled oscillator (DCO) coupled to the loop filter circuit and configured to modify the generated signal based on the first indication in a coarse mode and based on the second indication in a fine mode.