Wafer level package for device
AssigneeTeknologian tutkimuskeskus VTT Oy
InventorJae-Wung Lee
Life of this patent
Estimating the term…
Abstract
According to an example aspect of the present invention, there is provided a wafer level package (100) for a device, the package (100) comprising a first substrate (102) and a second substrate (103), at least one insulating stand-off structure (104) between the first substrate (102) and the second substrate (103), a bonding layer (108) on the at least one stand-off structure (104), and a first lateral electrical connection line (109) on a surface of the first substrate (102) and a second lateral electrical connection line (110) on a surface the second substrate (103), wherein electrical connection is formed between the first lateral electrical connection line (109) and the second lateral connection line (110) via the bonding layer (108) of the at least one stand-off structure (104).
Claims20
A wafer level package for a device, the package comprising:
- a first substrate and a second substrate,
- at least one insulating stand-off structure between the first substrate and the second substrate,
- a bonding layer on the at least one insulating stand-off structure, and
- a first lateral electrical connection line on a surface of the first substrate and a second lateral electrical connection line on a surface of the second substrate,
- wherein electrical connection is formed between the first lateral electrical connection line and the second lateral electrical connection line via the bonding layer of the at least one insulating stand-off structure, and
- wherein the bonding layer comprises a eutectic alloy.
A wafer level package for a MEMS device, the package comprising:
- a MEMS device wafer;
- a first lateral electrical connection line on a surface of the MEMS device wafer;
- a cap wafer;
- a second lateral electrical connection line on a surface of the cap wafer;
- at least one insulating stand-off structure between the MEMS device wafer and the cap wafer;
- and
- a bonding layer on the at least one insulating stand-off structure;
- wherein the first lateral electrical connection line is electrically connected to the second lateral electrical connection line via the bonding layer of the at least one insulating stand-off structure.
A wafer level package for a device, the package comprising:
- a first substrate;
- a first lateral electrical connection line on a surface of the first substrate;
- a second substrate;
- a second lateral electrical connection line on a surface of the second substrate;
- at least one insulating stand-off structure between the first substrate and the second substrate;
- a bonding layer on the at least one insulating stand-off structure, the bonding layer comprising a eutectic alloy, and the bonding layer electrically connecting the first lateral electrical connection line to the second lateral electrical connection line.
Dependencies are inferred from the claim text.