Gate-controlled diode and electronic circuit
AssigneeMitsubishi Electric Corporation
InventorAyanori Gatto
Life of this patent
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Abstract
An object is to increase a tolerance of a gate pulse width in a gate-controlled diode while suppressing detrimental effects on other main electrical characteristics. A gate-controlled diode includes: a diode gate electrode buried in each of first trenches through an oxide film in a first active region; an anode electrode buried in each of second trenches through the oxide film in a second active region; a P type channel layer formed in a surface layer of an N− type semiconductor substrate; and an N+ type layer formed in a surface layer of the P type channel layer in the first active region. An area of the first active region is 20% or higher and 80% or lower of a sum of the area of the first active region and an area of the second active region.
Claims5
A gate-controlled diode, comprising:
- a semiconductor substrate of a first conductivity type;
- an active region formed in a first main surface of the semiconductor substrate;
- a cathode layer of the first conductivity type formed in a second main surface of the semiconductor substrate, the second main surface being a main surface opposite to the first main surface;
- and
- a buffer layer of the first conductivity type formed between the cathode layer and the semiconductor substrate,
- wherein the active region is divided into a first active region and a second active region in a plan view,
- the gate-controlled diode, further comprising:
- a plurality of first trenches formed at regular intervals in the first main surface of the semiconductor substrate in the first active region;
- a diode gate electrode buried in each of the first trenches through an oxide film;
- a plurality of second trenches formed at regular intervals in the first main surface of the semiconductor substrate in the second active region;
- an anode electrode buried in each of the second trenches through the oxide film;
- a channel layer of a second conductivity type formed in a surface layer of the semiconductor substrate between adjacent two of the first trenches and between adjacent two of the second trenches, the channel layer being electrically connected to the anode electrode;
- and
- a layer of the first conductivity type formed in a surface layer of the channel layer in the first active region,
- wherein an area of the first active region is 20% or higher and 80% or lower of a sum of the area of the first active region and an area of the second active region.
Dependencies are inferred from the claim text.