Low leakage multiplexer

A method comprising:

• receiving, at ones of a plurality of switch circuits coupled between an output node and corresponding ones of a plurality of input nodes, corresponding input signals;
• selecting a particular one of the plurality of switch circuits to provide its corresponding input signal from its corresponding input node to the output node;
• activating, in the particular one of the plurality of switch circuits, a first switch element and a second switch element of the particular one of the plurality of switch circuits, wherein the first switch element is coupled between its corresponding input node and an intermediate node, and wherein the second switch element is coupled between the intermediate node and the output node;
• generating, using a buffer circuit and a voltage level of the output node, a buffered voltage;
• and
• providing the buffered voltage to respective intermediate nodes of unselected ones of the plurality of switch circuits;
• wherein activating the first and second switch elements of the particular one of the plurality of switch circuits comprises generating and providing, by a first subset of a plurality of driver circuits and to the first and second switch elements, a first plurality of selection signals having a first voltage swing;
• and
• wherein providing the buffered voltage to respective intermediate nodes of unselected ones of the plurality of switch circuits comprises generating and providing, by a second subset of a plurality of driver circuits and to a third switch element of the unselected ones of the plurality of switch circuits, a second plurality of selection signals having a second voltage swing different from the first voltage swing.

A system comprising:

• a plurality of functional circuit blocks, wherein two or more of the plurality of functional circuit blocks are configured to generate corresponding ones of a plurality of test signals;
• a multiplexer configured to provide a selected one of the plurality of test signals to an output node;
• and
• a buffer circuit configured to generate a buffered voltage using a voltage level of the output node;
• wherein the multiplexer comprises a plurality of switch circuits coupled between respective ones of a plurality of input nodes and the output node, wherein a first switch circuit includes:
• a first pass gate coupled between a respective one of the plurality of input nodes and an intermediate node;
• a second pass gate coupled between the intermediate node and the output node;
• and
• a third pass gate coupled between an output of the buffer circuit and the intermediate node;
• and
• a plurality of driver circuits including a first subset and a second subset, wherein driver circuits of the first subset are configured to generate and provide, to the third switch pass gates of ones of the plurality of switch circuits, a first plurality of selection signals having a first voltage swing, and wherein driver circuits of the second subset are configured to generate and provide, to the third pass gates of the plurality of switch circuits, a second plurality of selection signals having a second voltage swing, wherein the second voltage swing is less than the first voltage swing;
• wherein, when selected, the first switch circuit is configured to activate the first and second pass gates and de-activate the third pass gate, and wherein, when a different one of the plurality of switch circuits is selected, the first switch circuit is configured to de-activate the first and second pass gates and activate the third pass gate.