US 12,744,528 B2 · Clock transmission circuit

Abstract

A clock transmission circuit including a first inverter configured to inversion-drive a first transmission node in response to a first clock signal, among differential clock signals that are loaded onto a first reception node, a second inverter configured to inversion-drive a second transmission node in response to a second clock signal, among the differential clock signals that are loaded onto a second reception node, a first additional driver configured to additionally drive the first transmission node in response to the second clock signal that is loaded onto the second reception node, and a second additional driver configured to additionally drive the second transmission node in response to the first clock signal that is loaded onto the first reception node.

Claims18

Dependent claims

A clock transmission circuit comprising:

a first inverter configured to inversion-drive a first transmission node in response to a first clock signal, among differential clock signals that are loaded onto a first reception node;
a second inverter configured to inversion-drive a second transmission node in response to a second clock signal, among the differential clock signals that are loaded onto a second reception node;
a first additional driver configured to additionally drive the first transmission node in response to the second clock signal that is loaded onto the second reception node, and having a driving force less than a driving force of the first inverter;
and
a second additional driver configured to additionally drive the second transmission node in response to the first clock signal that is loaded onto the first reception node, and having a driving force less than a driving force of the second inverter.

2 more elements

A clock transmission circuit comprising:

a first transmission circuit configured to transmit a first clock signal, among differential clock signals, through a plurality of first inverters that are connected in a chain form;
a second transmission circuit configured to transmit a second clock signal, among the differential clock signals, through a plurality of second inverters that are connected in a chain form and that correspond to the plurality of first inverters, respectively;
at least one first additional driver configured to additionally drive an output node of at least one second selected inverter corresponding to at least one first selected inverter, among the plurality of first inverters, in response to a signal that is loaded onto an input node of the at least one first selected inverter, among the plurality of second inverters;
and
at least one second additional driver configured to additionally drive an output node of the at least one first selected inverter in response to a signal that is loaded onto an input node of the at least one second selected inverter,
wherein a driving force of each first additional driver is less than a driving force of each second selected inverter, and
wherein a driving force of each second additional driver is less than a driving force of each first selected inverter.

4 more elements

Dependencies are inferred from the claim text.

Clock transmission circuit

Life of this patent

Clock transmission circuit

Life of this patent

Abstract

Claims18