Driving circuit and controlling method for power transistor

A driving circuit for a power transistor, the driving circuit comprising:

• a gate driving circuit configured to output a driving voltage signal, a pulse width modulation signal and a controlling signal;
• a controlling circuit comprising:
• a first transistor coupled to the gate driving circuit and selectively turned on or off according to the pulse width modulation signal;
• and
• a second transistor coupled to the gate driving circuit and selectively turned on or off according to the pulse width modulation signal and the controlling signal;
• the power transistor coupled to the gate driving circuit and the controlling circuit, and controlled by the driving voltage signal;
• wherein in response to determining that the first transistor is turned on or both the first transistor and the second transistor are turned on, the driving voltage signal is pulled to a target voltage level;
• wherein the first transistor comprises:
• a first gate terminal coupled to the gate driving circuit;
• a first drain terminal electrically connected to the gate driving circuit and a gate terminal of the power transistor;
• and
• a first source terminal forming a kelvin connection with a source terminal of the power transistor;
• wherein the second transistor comprises:
• a second gate terminal coupled to the gate driving circuit;
• a second drain terminal electrically connected to the gate driving circuit and the gate terminal of the power transistor;
• and
• a second source terminal forming the kelvin connection with the source terminal of the power transistor.

A controlling method of a driving circuit for a power transistor, the controlling method comprising:

• a signal outputting step comprising:
• configuring a gate driving circuit to output a driving voltage signal and a pulse width modulation signal;
• and
• configuring one of the gate driving circuit and a voltage controller to output a controlling signal;
• a first transistor controlling step comprising controlling the first transistor to selectively turn on or off according to the pulse width modulation signal;
• a second transistor controlling step comprising controlling the second transistor to selectively turn on or off according to the pulse width modulation signal and the controlling signal;
• and
• a power transistor controlling step comprising controlling the power transistor according to the driving voltage signal;
• wherein in response to determining that the first transistor is turned on or both the first transistor and the second transistor are turned on, the driving voltage signal is pulled to a target voltage level;
• wherein the first transistor comprises:
• a first gate terminal coupled to the gate driving circuit;
• a first drain terminal electrically connected to the gate driving circuit and a gate terminal of the power transistor;
• and
• a first source terminal forming a kelvin connection with a source terminal of the power transistor;
• wherein the second transistor comprises:
• a second gate terminal coupled to the one of the gate driving circuit and the voltage controller;
• a second drain terminal electrically connected to the gate driving circuit and the gate terminal of the power transistor;
• and
• a second source terminal forming the kelvin connection with the source terminal of the power transistor.