Semiconductor integrated circuit and memory system

A semiconductor integrated circuit comprising:

• a first pulse generator that generates a first pulse signal based on a first signal, and a second pulse signal that is an inverted signal of the first pulse signal;
• a second pulse generator that generates a third pulse signal based on a second signal, and a fourth pulse signal that is an inverted signal of the third pulse signal;
• a first inversion buffer that outputs a third signal from a first node, based on inputs of the first pulse signal and the third pulse signal;
• and
• a second inversion buffer that outputs a fourth signal from a second node, based on inputs of the second pulse signal and the fourth pulse signal, wherein,
• when a logic level of the first pulse signal changes from a first logic level to a second logic level different from the first logic level, the first inversion buffer changes a logic level of the third signal from the second logic level to the first logic level, and, when a logic level of the third pulse signal changes from the second logic level to the first logic level, the first inversion buffer changes the logic level of the third signal from the first logic level to the second logic level, and,
• when a logic level of the second pulse signal changes from the second logic level to the first logic level, the second inversion buffer changes a logic level of the fourth signal from the first logic level to the second logic level, and, when a logic level of the fourth pulse signal changes from the first logic level to the second logic level, the second inversion buffer changes the logic level of the fourth signal from the second logic level to the first logic level.