Integrated circuit and method of forming the same

A flip-flop comprising:

• a first set of transistors of a first type being located in a first row, the first row extending in a first direction;
• a second set of transistors of a second type being located in a second row different from the first row, the second row extending in the first direction and being separated from the first row in a second direction different from the first direction, the second type being different from the first type;
• and
• a third set of transistors of the second type being located in a third row different from the first row and the second row, the third row extending in the first direction and being separated from the first row and the second row in the second direction;
• wherein the first set of transistors and the second set of transistors include a first master latch circuit and a first slave latch circuit, and the first master latch circuit and the first slave latch circuit are separated from each other in the first direction by at least a first distance;
• wherein the third set of transistors include a second slave latch circuit and a second master latch circuit, and the second slave latch circuit and the second master latch circuit are separated from each other in the first direction by at least a second distance;
• and
• wherein the first master latch circuit and the first slave latch circuit are coupled together, and the second master latch circuit and the second slave latch circuit are coupled together.

A method of fabricating a flip-flop, the method comprising:

• forming a first set of transistors of a first type in a first row, the first row extending in a first direction;
• forming a second set of transistors of a second type in a second row, the second row extending in the first direction and being separated from the first row in a second direction different from the first direction, the second type being different from the first type, wherein the first set of transistors and the second set of transistors include a first master latch circuit and a first slave latch circuit, and the first master latch circuit and the first slave latch circuit are separated from each other in the first direction by a first distance;
• forming a third set of transistors of the second type in a third row, the third row extending in the first direction;
• forming a fourth set of transistors of the first type in a fourth row, the fourth row extending in the first direction and being separated from the third row in the second direction, wherein the third set of transistors and the fourth set of transistors include a second master latch circuit and a second slave latch circuit, and the second master latch circuit and the second slave latch circuit are separated from each other in the first direction by a second distance;
• and
• electrically coupling the first master latch circuit and the second master latch circuit together.