One time programming memory including forksheet transistors and using physically unclonable function technology

A one time programming memory using a physically unclonable function technology, the one time programming memory comprising a first memory cell and a second memory cell, the first memory cell and the second memory cell being respectively located beside a first side and a second side of an isolation wall, the first memory cell comprising:

• a first nanowire, wherein a first-portion surface of the first nanowire is contacted with the isolation wall;
• a first gate structure comprising a first gate dielectric layer, a first gate layer, a first spacer and a second spacer, wherein a central region of a second-portion surface of the first nanowire is covered by the first gate dielectric layer, a first side region of the second-portion surface of the first nanowire is contacted with the first spacer, a second side region of the second-portion surface of the first nanowire is contacted with the second spacer, the first gate dielectric layer is covered by the first gate layer, and the first gate layer is connected with a first antifuse line;
• a second nanowire, wherein a first-portion surface of the second nanowire is contacted with the isolation wall;
• a second gate structure comprising a second gate dielectric layer, a second gate layer, a third spacer and a fourth spacer, wherein a central region of a second-portion surface of the second nanowire is covered by the second gate dielectric layer, a first side region of the second-portion surface of the second nanowire is contacted with the third spacer, a second side region of the second-portion surface of the second nanowire is contacted with the fourth spacer, the second gate dielectric layer is covered by the second gate layer, and the second gate layer is connected with a second antifuse line;
• a first drain/source structure electrically connected with a first terminal of the first nanowire;
• a second drain/source structure electrically connected with a second terminal of the first nanowire and a first terminal of the second nanowire;
• and
• a third drain/source structure electrically connected with a second terminal of the second nanowire;
• a first select transistor, wherein a first drain/source terminal of the first select transistor is coupled to the first drain/source structure, a gate terminal of the first select transistor is connected with a first word line, and a second drain/source terminal of the first select transistor is connected with a first bit line;
• and
• a second select transistor, wherein a first drain/source terminal of the second select transistor is coupled to the third drain/source structure, a gate terminal of the second select transistor is connected with a second word line, and a second drain/source terminal of the second select transistor is connected with a second bit line,
• wherein the first nanowire, the first gate structure, the first drain/source structure and the second drain/source structure are collaboratively formed as a first antifuse transistor, and the second nanowire, the second gate structure, the second drain/source structure and the third drain/source structure are collaboratively formed as a second antifuse transistor,
• wherein when an enroll action is performed, a region between the first antifuse line and the first bit line is a first enroll path, and a region between the second antifuse line and the second bit line is a second enroll path, wherein when an enroll action is performed, the first enroll path and the second enroll path are turned on, so that one of the first gate dielectric layer and the second gate dielectric layer is ruptured,
• wherein when a read action is performed, the region between the first antifuse line and the first bit line is a first read path, and the region between the second antifuse line and the second bit line is a second read path, wherein the read action is performed, a one-bit random code is determined.