Memory device including semiconductor element
AssigneeUnisantis Electronics Singapore Pte. Ltd.
InventorsKoji Sakui, Nozomu Harada
Life of this patent
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Abstract
A plurality of dynamic flash memory cells are arranged in a matrix on a substrate, a first dynamic flash memory cell and a second dynamic flash memory cell overlap each other in a vertical direction or horizontal direction of a substrate, and voltages applied to a select gate line common to the memory cells, a plate line, a first bit line and a second bit line that are independent, and a source line are controlled to perform a data erase operation of the first and second dynamic flash memory cells, an independent data write operation or data write prohibition operation of the first and second dynamic flash memory cells, and a data read operation of the first and second dynamic flash memory cells.
Claims15
A memory device including a semiconductor element, the memory device further comprising:
- a plurality of semiconductor memory cells arranged in a matrix on a substrate, the semiconductor memory cells including a first memory cell and a second memory cell, the first memory cell including a first semiconductor base material extending in a vertical direction or a horizontal direction with respect to the substrate, the second memory cell including a second semiconductor base material separated from the first semiconductor base material in the vertical direction or the horizontal direction and overlapping the first semiconductor base material in a plan view in the case of separation in the vertical direction or in a sectional view in the case of separation in the horizontal direction;
- a first impurity region and a second impurity region connected to respective ends of the first semiconductor base material;
- a third impurity region and a fourth impurity region connected to respective ends of the second semiconductor base material;
- a first gate insulating layer being in contact with a side surface facing the second semiconductor base material among side surfaces of the first semiconductor base material, and a second gate insulating layer being in contact with a side surface facing the first semiconductor base material among side surfaces of the second semiconductor base material;
- and
- a first gate conductor layer and a second gate conductor layer being in contact with the first and second gate insulating layers and separated from each other, wherein
- the first and third impurity regions are connected to a source line, the second impurity region is connected to a first bit line, the fourth impurity region is connected to a second bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a select gate line, and the other is connected to a plate line.
Dependencies are inferred from the claim text.