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AssigneeSynopsys, Inc.
InventorsShailesh Kumar Chauhan, Akhil Thotli, Kailash Kumar, Ankit Agrawal
Estimating the term…
Failsafe IO circuitry is provided that can operate in a failsafe mode and a normal mode. The failsafe IO circuitry can include input circuitry that (i) receives a pad signal (PAD) from driver circuitry, (ii) receives control signals (VDDIO, VREFN) and (iii) provides an output signal (PADBY2) generated based on the received control signals (VDDIO, VREFN), wherein, when operating in a normal mode, the pad signal (PAD) is a floating signal and the output signal (PADBY2) is 0 volts (0V), and power gated logic circuitry that (i) receives the output signal (PADBY2) from the input circuitry, (ii) receives the control signals (VDDIO, VREFN) and (iii) outputs a reference pad failsafe signal (PAD_FS), wherein, when operating in the normal mode, the reference pad failsafe signal (PAD_FS) is 0V.
Circuitry, comprising:
A method of supplying signals to failsafe logic circuitry, the method comprising:
A non-transitory computer readable medium comprising stored instructions for supplying signals to failsafe logic circuitry, the instructions, when executed by a processor, cause the processor to:
Dependencies are inferred from the claim text.