Edge combiners with symmetrical operation range at high speed

A method of edge combining in an electronic timing system, the method comprising:

• controlling a first input of a circuit state element based on a first timing signal;
• receiving a second timing signal as an input to a pulse generator, and resetting the circuit state element by controlling a second input of the circuit state element with the pulse generator;
• delaying a data output signal from a data output of the circuit state element to generate a delayed data output signal using a first delay circuit;
• and
• generating an output signal having a pulse width indicating a delay between an edge of the first timing signal and an edge of the second timing signal using an output logic circuit that receives the data output signal at a first input through a first signal path that does not include the first delay circuit and that receives the delayed data output signal at a second input through a second signal path that includes the first delay circuit, the pulse width of the output signal having a first edge arising from the edge of the first timing signal propagating to the first input of the output logic circuit through the circuit state element and the first signal path, and a second edge corresponding to the edge of the second timing signal propagating to the second input of the output logic circuit through the first pulse generator, the circuit state element, and the second signal path.

A time of flight system comprising:

• an edge combiner comprising:
• a circuit state element including a first input controlled by a first timing signal, a second input, and a data output;
• a pulse generator configured to receive a second timing signal and to reset the circuit state element based on the second timing signal;
• a first delay circuit;
• and
• an output logic circuit including a first input connected to the data output of the circuit state element through a first signal path that does not include the first delay circuit, a second input connected to the data output of the circuit state element through a second signal path that includes the first delay circuit, and an output configured to generate an output signal having a pulse width indicating a delay between an edge of the first timing signal and an edge of the second timing signal, the pulse width of the output signal having a first edge arising from the edge of the first timing signal propagating to the first input of the output logic circuit through the circuit state element and the first signal path, and a second edge corresponding to the edge of the second timing signal propagating to the second input of the output logic circuit through the first pulse generator, the circuit state element, and the second signal path;
• and
• a driver circuit configured to control an emission of light from a light emitting element based on the output signal.