Clock data recovery circuit and phase selector/phase interpolator circuit thereof, and electronic device

A clock data recovery circuit, comprising:

• a phase selector/phase interpolator circuit, comprising:
• two phase selector circuits, respectively connected to a controller of the clock data recovery circuit, each of the two phase selector circuits configured to select and output one of N first clock signals of different phases received according to a first code signal output by the controller, wherein N≥2, and wherein each of the two phase selector circuits comprises:
• N first tail current tubes which are respectively configured to output a tail current of corresponding magnitude according to a first bias voltage, wherein the tail current changes in a positive correlation with the first bias voltage;
• N phase selector units, wherein each of the N phase selector units is connected to one of the N first tail current tubes and two output ends of the phase selector circuit, each two of the phase selector units receive two first clock signals, and the first code signal is respectively received by the N phase selector units, and each of the N phase selector units is configured to convert the two first clock signals into two output clock signals according to the first code signal and output the two output clock signals to the two output ends of the phase selector circuit, wherein the two output clock signals have same frequencies and phases as the two first clock signals;
• a current source circuit which is connected in series to the two output ends of the phase selector circuit, and the current source circuit serves as a load of the phase selector circuit;
• and
• a comparison circuit which is connected to the two output ends of the phase selector circuit and the N first tail current tubes, and configured to compare a common-mode voltage of the two output clock signals with a reference voltage and perform negative feedback regulation on a magnitude of the first bias voltage;
• and
• a phase interpolator circuit, respectively connected to the controller and the two phase selector circuits, configured to receive the two first clock signals output from the two phase selector circuits and output a second clock signal after performing a weighted operation on the two first clock signals received according to a second code signal output by the controller.

An electronic device, comprising:

• a clock data recovery circuit, comprising:
• a phase selector/phase interpolator circuit, comprising:
• two phase selector circuits, respectively connected to a controller of the clock data recovery circuit, each of the two phase selector circuits configured to select and output one of N first clock signals of different phases received according to a first code signal output by the controller, wherein N≥2, and wherein each of the two phase selector circuits comprises:
• N first tail current tubes which are respectively configured to output a tail current of corresponding magnitude according to a first bias voltage, wherein the tail current changes in a positive correlation with the first bias voltage;
• N phase selector units, wherein each of the N phase selector units is connected to one of the N first tail current tubes and two output ends of the phase selector circuit, each two of the phase selector units receive two first clock signals, and the first code signal is respectively received by the N phase selector units, and each of the N phase selector units is configured to convert the two first clock signals into two output clock signals according to the first code signal and output the two output clock signals to the two output ends of the phase selector circuit, wherein the two output clock signals have same frequencies and phases as the two first clock signals;
• a current source circuit which is connected in series to the two output ends of the phase selector circuit, and the current source circuit serves as a load of the phase selector circuit;
• and
• a comparison circuit which is connected to the two output ends of the phase selector circuit and the N first tail current tubes, and configured to compare a common-mode voltage of the two output clock signals with a reference voltage and perform negative feedback regulation on a magnitude of the first bias voltage;
• and
• a phase interpolator circuit, respectively connected to the controller and the two phase selector circuits, configured to receive the two first clock signals output from the two phase selector circuits and output a second clock signal after performing a weighted operation on the two first clock signals received according to a second code signal output by the controller.