Integrated circuit and method of operating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsBei-Shing Lien, Szu-Lin Liu
Life of this patent
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Abstract
An integrated circuit is provided, which includes a first temperature-sensitive device and a second temperature-sensitive device. The first temperature-sensitive device is configured to generate a first bias current which monotonically increases in accordance with an absolute temperature, and generate a first voltage based on the first bias current. The second temperature-sensitive device is configured to generate a second voltage across the second temperature-sensitive device, and output a reference voltage at an output terminal of the integrated circuit. The second voltage monotonically decreases in accordance with the absolute temperature. The reference voltage equals the first voltage plus the second voltage.
Claims20
An integrated circuit, comprising:
- a first temperature-sensitive device configured to generate a first bias current which monotonically increases in accordance with an absolute temperature of the integrated circuit, and generate a first voltage based on the first bias current;
- and
- a second temperature-sensitive device configured to generate a second voltage across the second temperature-sensitive device, and output a reference voltage at an output terminal of the integrated circuit,
- wherein the second voltage monotonically decreases in accordance with the absolute temperature of the integrated circuit,
- wherein the reference voltage is equal to a sum of the first voltage and the second voltage,
- wherein the first temperature-sensitive device comprises:
- a first cascode structure comprising:
- a first stacked gate device having a gate terminal connected to a first node, a first terminal connected to a second node, and a second terminal connected to a ground voltage;
- and
- a second stacked gate device having a gate terminal connected to the first node, a first terminal connected to the first node, and a second terminal connected to the second node;
- and
- a second cascode structure comprising:
- a third stacked gate device having a gate terminal connected to the first node, a first terminal connected to a third node, and a second terminal connected to a fourth node;
- and
- a fourth stacked gate device having a gate terminal connected to the first node, a first terminal connected to a fifth node, and a second terminal connected to the third node.
An integrated circuit, comprising:
- a first cascode structure configured to generate a first bias current that is proportional to an absolute temperature of the integrated circuit;
- a first current mirror configured to generate a second bias current in response to the first bias current;
- a second cascode structure coupled to the first cascode structure, and configured to generate a first voltage at a first node in response to the second bias current;
- a second current mirror configured to generate a third bias current in response to the first bias current, wherein the third bias current is proportional to the absolute temperature of the integrated circuit;
- and
- a first stacked gate device coupled between the first node and an output terminal of the integrated circuit, and configured to receive the third bias current, generate a second voltage across the first stacked gate device, and output a reference voltage at the output terminal of the integrated circuit;
- wherein the second voltage is complementary to the absolute temperature of the integrated circuit,
- wherein the reference voltage is equal to a sum of the first voltage and the second voltage.
A method, comprising:
- generating a first bias current passing through a first cascode structure and a resistor;
- generating, based on the first bias current, a second bias current passing through a second cascode structure;
- generating, based on the first bias current, a third bias current passing through a temperature-sensitive device and a first stacked gate device within the second cascode structure;
- outputting a reference voltage generated at a terminal of the temperature-sensitive device;
- generating a first voltage by the second cascode structure in response to the second bias current;
- and
- generating, by the temperature-sensitive device, a second voltage across the temperature-sensitive device;
- wherein the first voltage is proportional to an absolute temperature, and the second voltage is complementary to the absolute temperature,
- wherein the reference voltage is a sum of the first voltage and the second voltage.
Dependencies are inferred from the claim text.