Semiconductor module

A semiconductor module comprising:

• first and second switching elements connected in series between a first potential and a second potential lower than the first potential and operating in a complementary manner;
• a high potential side drive circuit including a first driver connected to a first gate of the first switching element, the high potential side drive circuit being configured to receive an input of a first drive signal and configured to provide a first output to the first gate;
• and
• a low potential side drive circuit including a second driver connected to a second gate of the second switching element, the low potential side drive circuit being configured to receive an input of a second drive signal and configured to provide a second output to the second gate,
• the high potential side drive circuit including:
• first reception terminals configured to receive a first data signal, an enable signal, and a first clock signal, respectively;
• a first shift register composed of a first plurality of cascaded flip-flops, the first data signal being configured to be recorded in the first plurality of flip-flops in response to the first clock signal and the enable signal, whenever the first data signal is recorded in the first plurality of flip-flops, first data having been recorded in the first plurality of flip-flops being configured to be moved to adjacent flip-flops among the first plurality of flip-flops;
• a first set value holding unit operative in response to the enable signal to extract and record contents recorded in the first plurality of flip-flops of the first shift register;
• a first decoder configured to cause a first current outputting capability of the first driver to be variable according to the recording of the first set value holding unit;
• and
• a first output terminal configured to output the first clock signal to the low potential side drive circuit as a second clock signal,
• the low potential side drive circuit including:
• second reception terminals to receive a second data signal, the enable signal, and the second clock signal, respectively;
• a second shift register composed of a second plurality of cascaded flip-flops, the second data signal being configured to be recorded in the second plurality of flip-flops in response to the second clock signal and the enable signal, whenever the second data signal is recorded in the second plurality of flip-flops, second data having been recorded in the second plurality of flip-flops being configured to be moved to adjacent flip-flops among the second plurality of flip-flops;
• a second set value holding unit operative in response to the enable signal to extract and record contents recorded in the second plurality of flip-flops of the second shift register;
• a second decoder configured to cause a second current outputting capability of the second driver to be variable according to the recording of the second set value holding unit;
• and
• a second output terminal configured to output the second data signal that is held in a flip-flop of a last stage of the second shift register to the high potential side drive circuit as the first data signal.