Level shifting device and method

A circuit, comprising:

• a current source configured to generate a bias current;
• a first diode-connected transistor coupled in series with a diode between a high supply potential node and a first node biased by said bias current to generate a first DC voltage;
• a mirror transistor coupled to the first transistor and configured to generate a mirror bias current;
• a second diode-connected transistor coupled in series with a diode between a low supply potential node and a second node biased by said mirror bias current to generate a second DC voltage;
• a first output transistor and a second output transistor connected at an output node, wherein the first and second output transistors are electrically in series between the high supply potential node and the low supply potential node;
• a first transistor control circuit powered between the high supply potential node and a ground node, wherein the first transistor control circuit generates a first control signal applied to a control terminal of the first output transistor, said first control signal having a voltage level limit controlled by the first DC voltage;
• and
• a second transistor control circuit powered between the high supply potential node and the low supply potential node, wherein the second transistor control circuit generates a second control signal applied to a control terminal of the second output transistor, said second control signal having a voltage level limit controlled by the second DC voltage.

A circuit, comprising:

• a first p-type transistor and a second n-type transistor connected at a first node configured to deliver an output potential level, wherein the first p-type transistor and second n-type transistor are electrically in series between a high supply potential node and a low supply potential node;
• a first voltage generator coupled to the high supply potential node and configured to generate a first DC voltage referenced to the high supply potential node in response to a first bias current, wherein said first DC voltage controls a voltage limit referenced to the high supply potential node for a control voltage applied to a control terminal of the first p-type transistor by a first transistor control circuit;
• and
• a second voltage generator coupled to the low supply potential node and configured to generate a second DC voltage referenced to the low supply potential node in response to a second bias current derived from the first bias current, wherein said second DC voltage controls a voltage limit referenced to the low supply potential node for a control voltage applied to a control terminal of the second n-type transistor by a second transistor control circuit.