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US 12,732,167 B2Granted
Robust single event upset (SEU) tolerant high-performance flip-flop
AssigneeXilinx, Inc.
InventorsTabrez Alam, Kumar Rahul, Santosh Yachareni, Ishtiaque Ahmad
Life of this patent
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Abstract
Embodiments herein describe single event upset (SEU) tolerant flip-flop that includes master latch circuitry, slave latch circuitry, and a tristate driver having an input coupled to an output of the master latch circuitry and an output coupled to a first data input of the slave latch circuitry, where the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the output of the master latch circuitry.
Claims19
An integrated circuit, comprising:
- a master-slave latch circuit comprising:
- master latch circuitry comprising a data input configured to receive data and a data output configured to output the data;
- slave latch circuitry;
- and
- a first tristate driver comprising a data input configured to receive the data from the data output of the master latch circuitry, and a data output coupled to a first data input of the slave latch circuitry;
- wherein the first tristate driver comprises:
- an inverter circuit configured to invert the data output of the master latch circuitry;
- a pull-up transistor configured to provide a supply voltage to the inverter circuit based on a first clock;
- and
- a pull-down transistor configured to provide a reference voltage to the inverter circuit based on an inverse of the first clock;
- and
- wherein the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the data output of the master latch circuitry.
9 more elements
An integrated circuit, comprising:
- a master-slave latch circuit comprising master latch circuitry, slave latch circuitry, and a first tristate driver having a data input coupled to a data output of the master latch circuitry and a data output coupled to a first data input of the slave latch circuitry;
- wherein the first tristate driver comprises:
- a first inverter circuit configured to invert the data output of the master latch circuitry;
- a first pull-up transistor configured to provide a supply voltage to the first inverter circuit based on a first clock;
- and
- a first pull-down transistor configured to provide a reference voltage to the first inverter circuit based on an inverse of the first clock;
- and
- wherein the master-slave latch circuit is configured as a single event upset (SEU) tolerant flip-flop
- wherein the first tristate driver is configured to increase a static noise margin of an internal latch node of the master latch circuitry.
6 more elements
An integrated circuit device, comprising:
- a field-programmable gate array (FPGA), comprising random access memory (RAM) circuitry, wherein the RAM circuitry comprises a dual double interlocked storage cell (DICE), and wherein the DICE comprises master latch circuitry comprising a data input configured to receive data and a data output configured to output the data, slave latch circuitry, and a first tristate driver having a data input coupled to the data output of the master latch circuitry and a data output coupled to a first data input of the slave latch circuitry;
- wherein the first tristate driver is configured to inhibit charge transfer from the first data input of the slave latch circuitry to the data output of the master latch circuitry.
Dependencies are inferred from the claim text.