Spacer film scheme for polarization improvement
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTzu-Yu Lin, Yao-Wen Chang
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to an integrated chip. The integrated chip includes a lower electrode and a high-k dielectric material disposed over the lower electrode. An upper electrode is disposed over a central region of the high-k dielectric material and a dielectric spacer is arranged on a peripheral region of the high-k dielectric material. The high-k dielectric material includes non-zero concentrations of a tetragonal phase and a monoclinic phase. The non-zero concentrations of the tetragonal phase and the monoclinic phase are lower than a concentration of orthorhombic phase within the high-k dielectric material.
Claims20
An integrated chip, comprising:
- a lower electrode;
- a high-k dielectric material disposed over the lower electrode;
- an upper electrode disposed over a central region of the high-k dielectric material;
- and
- a dielectric spacer arranged on a peripheral region of the high-k dielectric material, wherein the high-k dielectric material comprises non-zero concentrations of a tetragonal phase and a monoclinic phase, the non-zero concentrations of the tetragonal phase and the monoclinic phase being lower than a concentration of orthorhombic phase within the high-k dielectric material.
An integrated chip, comprising:
- a lower electrode;
- a dielectric data storage structure disposed over the lower electrode;
- an upper electrode disposed over a central region of the dielectric data storage structure;
- and
- a dielectric spacer arranged over a peripheral region of the dielectric data storage structure, wherein the dielectric data storage structure has a minimum orthorhombic phase concentration that is greater than approximately 40%.
A method of forming an integrated chip (IC), comprising:
- forming a lower electrode layer over a substrate;
- forming a high-k data storage layer over the lower electrode layer;
- forming an upper electrode over the high-k data storage layer;
- forming one or more stressed sidewall spacers laterally surrounding the upper electrode;
- increasing an orthorhombic phase concentration within parts of the high-k data storage layer after forming the one or more stressed sidewall spacers;
- and
- patterning the high-k data storage layer and the lower electrode layer outside of the upper electrode and the one or more stressed sidewall spacers to form a high-k data storage structure and a lower electrode.
Dependencies are inferred from the claim text.