Error detection and correction method and circuit

An error detection and correction system, comprising:

• a pipeline circuit, operated at a first operating frequency, the pipeline circuit comprising:
• a first pipeline stage circuit, a first error detection and correction circuit coupled to the first pipeline stage circuit, a second pipeline stage circuit coupled to the first error detection and correction circuit, and a second error detection and correction circuit coupled to the second pipeline stage circuit, wherein each of the first and second error detection and correction circuits comprises:
• a master latch circuit configured to receive an input data and generate a sampling data;
• an error detection circuit coupled to the master latch circuit to compare the input data with the sampling data to generate a comparison result;
• a multiplexer coupled to the master latch circuit and the error detection circuit;
• and a slave latch circuit coupled to the multiplexer to receive a multiplexer output from the multiplexer and generate an output data, wherein, the multiplexer outputs the input data or the sampling data to the slave latch circuit according to the comparison result,
• a system error detection and correction circuit coupled to the pipeline circuit, wherein the system error detection and correction circuit comprises:
• a plurality of error state reception units, each receiving an error state signal from the error detection circuit;
• a plurality of continuous error state detection units coupled to adjacent error state reception units with continuous stages;
• a global system error detection unit coupled to the continuous error state detection units;
• and an interruption controller coupled to the global system error detection unit to interrupt and re-activate the pipeline circuit;
• when the continuous error state detection units detect continuous error states, the continuous error state detection units notify the global system error detection unit, the global system error detection unit stops all the operations of all pipeline stage circuits through the interruption controller and flushes the data of the pipeline stage circuits, and the pipeline circuit is re-activated at a second operating frequency, wherein the second operating frequency is lower than first operating frequency;
• and
• when the input data is identical to the sampling data, the multiplexer outputs the sampling data to the slave latch circuit;
• and, when the input data is different from the sampling data, the multiplexer outputs the input data to the slave latch circuit.