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US 12,727,142 B2Granted
Method for forming a SRAM memory cell structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHidehiro Fujiwara, Yi-Hsin Nien, Hung-Jen Liao
Life of this patent
Estimating the term…
Abstract
An apparatus includes memory cells. A first memory cell of the memory cells includes a first write port laid out in a first doping region and a first read port laid out in a second doping region. The first read port is separated from the first write port by a second write port of a second memory cell of the memory cells.
Claims20
A method for forming a SRAM memory cell structure, comprising:
- forming a plurality of first write access transistors for a first memory cell within a first area;
- forming a plurality of first read access transistors for the first memory cell within a second area;
- forming a plurality of second write access transistors for a second memory cell within a third area between the first area and the second area, the first memory cell and the second memory cell being memory cells in adjacent rows of the same column of the memory cell structure;
- and
- forming a plurality of second read access transistors for the first memory cell within a fourth area, the first area being between the third area and the fourth area.
2 more elements
A method for forming a memory cell structure, comprising:
- forming a first memory cell and a second memory cell;
- forming a first write port, of the first memory cell, comprising a plurality of first write access transistors within a first area and laid out in a first doping region;
- forming a first read port, of the first memory cell, comprising a plurality of first read access transistors within a second area and laid out in a second doping region;
- forming a second write port, of the second memory cell, comprising a plurality of second write access transistors within a third area between the first area and the second area;
- and
- forming a second read port, of the first memory cell, comprising a plurality of second read access transistors within the first area and laid out in the first doping region.
3 more elements
A method for forming a semiconductor device, comprising:
- forming a first memory cell by:
- forming n-type transistors of a first storage unit in a first n-plus (NP) region;
- forming p-type transistors of the first storage unit in a first p-plus (PP) region between the first NP region and a second NP region;
- forming a plurality of first write access transistors of a first write port of the first memory cell within a first area in the first NP region or in the first PP region;
- forming a plurality of first read access transistors of a first read port of the first memory cell within a second area in the second NP region, the first area being separated from the second area by a third area comprising a plurality of second write access transistors of a second write port of a second memory cell;
- and
- forming a plurality of second read access transistors of a second read port of the first memory cell in the first NP region.
4 more elements
Dependencies are inferred from the claim text.