Threshold generation circuit, corresponding system and method

A system for generating an adaptive wake-up threshold, the system comprising:

• a signal generator;
• a processor;
• a general-purpose input/output (GPIO) pin;
• and
• a wake-up threshold generator,
• wherein the processor is configured to:
• drive the signal generator in a burst mode of operation, the burst mode comprising alternating wake-up phases and waiting time intervals, wherein the signal generator is switched on to cause a pulsed output signal at an output node of the signal generator to rise during a wake-up phase, wherein the signal generator is switched off and the pulsed output signal decreases over time during a waiting time interval following the wake-up phase, and wherein a subsequent wake-up phase is initiated in response to the pulsed output signal decreasing to a wake-up threshold during the waiting time interval, wherein the pulsed output signal decreases due to a discharge of a capacitive load coupled to the output node of the signal generator,
• set the GPIO pin to a high-impedance state during the waiting time intervals,
• read a value of the GPIO pin during the waiting time intervals,
• set the GPIO pin to a first value in response to the wake-up threshold being found to be higher than an upper bound, and
• set the GPIO pin to a second value in response to the wake-up threshold being found to be lower than a lower bound,
• wherein the wake-up threshold generator is coupled to the GPIO pin and configured to:
• decrease the wake-up threshold in response to the GPIO pin being set to the first value, and
• increase the wake-up threshold in response to the GPIO pin being set to the second value.

A method for generating an adaptive wake-up threshold, the method comprising:

• driving a signal generator in a burst mode of operation, the burst mode comprising alternating wake-up phases and waiting time intervals, wherein during a wake-up phase, the signal generator is switched on to cause a pulsed output signal to rise, during a waiting time interval following the wake-up phase, the signal generator is switched off and the pulsed output signal decreases over time, and a subsequent wake-up phase is initiated in response to the pulsed output signal decreasing to a wake-up threshold during the waiting time interval, wherein the pulsed output signal decreases due to a discharge of a capacitive load coupled to an output node of the signal generator;
• setting a general-purpose input/output (GPIO) pin to a high-impedance state during the waiting time intervals;
• reading a value of the GPIO pin during the waiting time intervals;
• setting the GPIO pin to a first value in response to the wake-up threshold being found to be higher than an upper bound;
• setting the GPIO pin to a second value in response to the wake-up threshold being found to be lower than a lower bound;
• decreasing the wake-up threshold in response to the GPIO pin being set to the first value;
• and
• increasing the wake-up threshold in response to the GPIO pin being set to the second value.