Variable slew rate hybrid gate drivers for power modules

A vehicle, comprising:

• a frame defining a body and a passenger cabin;
• a processing system coupled to a gate driver within the body and configured to send pulse width modulation (PWM) signals to the gate driver;
• a plurality of voltage sources in the gate driver under control of the PWM signals;
• a plurality of gate resistors in the gate driver under control of the PWM signals;
• a plurality of current sources in the gate driver under control of the PWM signals;
• and
• a polyphase inverter comprising, for each phase of a motor coupled to the inverter, one or more hybrid sets of switching transistors of different semiconductor technologies,
• wherein each of the current sources in the gate driver is coupled to a gate and at least one other terminal of a respective one of the hybrid sets of switching transistors,
• wherein each of the plurality of voltage sources and gate resistors in the gate driver is coupled to a gate and at least one other terminal of another respective one of the hybrid sets of switching transistors;
• and
• wherein the plurality of gate resistors and the plurality of current sources are configured to provide slew rate (SR) control of each respective phase of the inverter using respective variable gate resistance values and variable gate current values to compensate for the different semiconductor technologies in real time to reduce switching losses and improve inverter efficiency.

A hybrid gate driver apparatus for providing slew rate (SR) control of a power inverter module (PIM), comprising:

• a plurality of input terminals for receiving pulse-width-modulation (PWM) control signals transmitted from a processing system;
• and
• a plurality of voltage sources and a plurality of gate resistors controlled by the PWM signals and having outputs coupled to a gate of at least one transistor of a switch in the PIM, the transistor includes a single semiconductor technology, at least one of the plurality of voltage sources coupled to at least one other non-gate terminal of the transistor;
• and
• a plurality of current sources controlled by the PWM signals and having outputs coupled to the gate of the at least one transistor of the switch in the PM, at least one of the plurality of current sources coupled to the at least one other non-gate terminal of the transistor, wherein the plurality of gate resistors, the plurality of voltage sources, and the plurality of current sources are configured to provide the SR control of the PIM to compensate for the different semiconductor technologies in real time to reduce switching losses and improve PM efficiency.