Transient stabilized SOI FETs

A bias voltage generation circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the bias voltage generation circuit including:

• (a) a metal-oxide-semiconductor field effect transistor (MOSFET) having a drain, a source, a gate, a VDS characteristic, a VGS characteristic, and a signal path through the MOSFET between the drain and the source;
• and
• (b) a switch coupled in series with the signal path of the MOSFET, configured to selectively couple the signal path to a normal current flow path or to a trickle current path;
• wherein, in an active mode, the switch couples the signal path of the MOSFET to the normal current flow path;
• and
• wherein, in a standby mode, the switch couples the signal path of the MOSFET to the trickle current path.

A method for eliminating or reducing changes in accumulated charge in a bias generation circuit for an amplifier, the bias generation circuit fabricated on a silicon-on-insulator (SOI) substrate as part of an integrated circuit susceptible to accumulated charge, the method including:

• (a) providing a field effect transistor (FET) having a drain, a source, a gate, a VDS characteristic, a VGS characteristic, and a signal path through the FET between the drain and the source;
• (b) coupling a switch in series with the signal path of the FET, configured to selectively couple the signal path to a normal current flow path or to a trickle current path;
• (c) in an active mode, setting the switch to couple the signal path of the FET to the normal current flow path;
• and
• (d) in a standby mode, setting the switch to couple the signal path of the FET to the trickle current path, such that at least one of the VGS characteristic and the VDS characteristic of the FET are close to respective active mode operational voltages for the VGS characteristic and the VDS characteristic sufficient to reduce changes in accumulated charge.