US 12,719,472 B2Granted

Power-on reset circuit

AssigneeNXP B.V.

InventorsSanjay Kumar Wadhwa, Neha Goel, Sapna Sharma

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Abstract

A power-on reset (POR) circuit includes a first transistor and a stack of transistors. The first transistor generates an enable voltage based on a first supply voltage. The enable voltage is a reduced version of the first supply voltage and ramps up based on a ramp-up of the first supply voltage. The stack of transistors generates a control voltage. The control voltage is a reduced version of the enable voltage and ramps up based on the ramp-up of the enable voltage. The control voltage delays ramping of the enable voltage such that the enable voltage ramps up to a first threshold voltage associated with the stack of transistors in a first time period. Further, a reset signal generated by the POR circuit is asserted when the enable voltage exceeds the first threshold voltage at the end of the first time period.

Claims21

Dependent claims

A circuit comprising:

a power-on reset (POR) circuit comprising:
a first transistor comprising:
a first current terminal that is configured to receive a first supply voltage from a first supply voltage terminal;
a control terminal configured to receive a control voltage;
and
a second current terminal configured to generate an enable voltage;
a first capacitor coupled between the second current terminal of the first transistor and a second supply voltage terminal;
a stack of transistors comprising:
a first supply terminal configured to receive the first supply voltage;
a second supply terminal configured to receive a second supply voltage;
an input terminal that is coupled to the second current terminal of the first transistor, and configured to receive the enable voltage;
a first output terminal that is coupled to the control terminal of the first transistor, and configured to generate the control voltage;
and
a second output terminal configured to generate a trigger voltage based on the first supply voltage and the enable voltage;
a second transistor comprising:
a control terminal configured to receive the enable voltage;
a first current terminal coupled to the control terminal of the first transistor, wherein the first current terminal of the second transistor corresponds to the first output terminal of the stack of transistors;
and
a second current terminal corresponding to the second output terminal of the stack of transistors;
and
a logic circuit that is coupled to the second current terminal of the first transistor and the second output terminal of the stack of transistors, and configured to:
receive the enable voltage and the trigger voltage;
and
generate a reset signal based on the enable voltage and the trigger voltage.

21 more elements

A circuit comprising:

a power-on reset (POR) circuit comprising:
a first transistor comprising:
a first current terminal that is configured to receive a first supply voltage from a first supply voltage terminal;
a control terminal configured to receive a control voltage;
and
a second current terminal configured to generate an enable voltage;
a first capacitor coupled between the second current terminal of the first transistor and a second supply voltage terminal;
a stack of transistors comprising:
a first supply terminal configured to receive the first supply voltage;
a second supply terminal configured to receive a second supply voltage;
an input terminal that is coupled to the second current terminal of the first transistor, and configured to receive the enable voltage;
a first output terminal that is coupled to the control terminal of the first transistor, and configured to generate the control voltage;
and
a second output terminal configured to generate a trigger voltage based on the first supply voltage and the enable voltage;
and
a logic circuit that is coupled to the second current terminal of the first transistor and the second output terminal of the stack of transistors, and configured to:
receive the enable voltage and the trigger voltage;
and
generate a reset signal based on the enable voltage and the trigger voltage:
wherein the stack of transistors further comprises:
a second transistor comprising:
a control terminal configured to receive the enable voltage;
a first current terminal coupled to the control terminal of the first transistor, wherein the first current terminal of the second transistor corresponds to the first output terminal of the stack of transistors;
and
a second current terminal;
and
a third transistor comprising:
a control terminal configured to receive the enable voltage;
a first current terminal;
and
a second current terminal coupled to the first current terminal of the second transistor;
wherein the stack of transistors further comprises:
a fourth transistor comprising:
a control terminal configured to receive the enable voltage;
a first current terminal configured to receive the first supply voltage, wherein the first current terminal of the fourth transistor corresponds to the first supply terminal of the stack of transistors;
and
a second current terminal;
and
a fifth transistor comprising:
a control terminal configured to receive the enable voltage;
a first current terminal coupled to the second current terminal of the fourth transistor;
and
a second current terminal coupled to the second current terminal of the second transistor, and configured to generate the trigger voltage, wherein the coupling between the second current terminals of the second transistor and the fifth transistor corresponds to the second output terminal of the stack of transistors.

40 more elements

A circuit comprising:

a power-on reset (POR) circuit comprising:
a first transistor comprising:
a first current terminal configured to receive a first supply voltage from a first supply voltage terminal;
a control terminal configured to receive a control voltage;
and
a second current terminal configured to generate an enable voltage;
and
a stack of transistors coupled to the second current terminal and the control terminal of the first transistor, wherein the stack of transistors is configured to:
receive the enable voltage;
and
generate the control voltage and a trigger voltage,
(i) wherein when the enable voltage is less than a first threshold voltage associated with the stack of transistors, the control voltage increases based on an increase in the enable voltage, and the trigger voltage remains above a second supply voltage,
(ii) wherein when the control voltage increases, the enable voltage ramps up to the first threshold voltage in a first time period, and
(iii) wherein when the enable voltage equals the first threshold voltage at an end of the first time period, the trigger voltage falls to the second supply voltage, thereby asserting a reset signal of the POR circuit.

11 more elements

A circuit comprising:

a power-on reset (POR) circuit comprising:
a first transistor comprising:
a first current terminal that is configured to receive a first supply voltage from a first supply voltage terminal;
a control terminal configured to receive a control voltage;
and
a second current terminal configured to generate an enable voltage;
a first capacitor coupled between the second current terminal of the first transistor and a second supply voltage terminal;
a stack of transistors comprising:
a first supply terminal configured to receive the first supply voltage;
a second supply terminal configured to receive a second supply voltage;
an input terminal that is coupled to the second current terminal of the first transistor, and configured to receive the enable voltage;
a first output terminal that is coupled to the control terminal of the first transistor, and configured to generate the control voltage;
and
a second output terminal configured to generate a trigger voltage based on the first supply voltage and the enable voltage;
and
a logic circuit that includes a first input coupled to the second current terminal of the first transistor to receive the enable voltage, a second input coupled to the second output terminal of the stack of transistors to receive the trigger voltage, and an output configured to generate a reset signal based on the enable voltage and the trigger voltage.

13 more elements

Dependencies are inferred from the claim text.