Auto-optimized delay control for die-to-die receiver sampling

A method comprising:

• obtaining received data and a sampling clock at a delay detector;
• producing a charging signal by the delay detector, the charging signal having a first pulse width responsive to a delay between an edge of the received data and a rising edge of the sampling clock;
• producing a discharging signal by the delay detector, the discharging signal having a second pulse width responsive to a positive pulse width of the sampling clock;
• supplying a charging current to an integrator capacitor by a current source responsive to receiving the charging signal;
• supplying a discharging current to the integrator capacitor by a current sink responsive to receiving the discharging signal;
• developing an output voltage at the integrator capacitor responsive to the charging current and the discharging current;
• and
• modulating the delay of a received clock by a variable delay to produce the sampling clock responsive to receiving the output voltage at a control input.

An integrated circuit, comprising:

• a first die generating a data signal and a clock signal;
• a data channel coupled to receive the data signal from the first die;
• a clock channel coupled to receive the clock signal from the first die;
• a second die coupled to the data channel and the clock channel, the second die including:
• a delay optimizer that obtains a received clock and produces a sampling clock at an optimal delay value;
• and
• a sampling receiver that obtains received data and produces sampled data responsive to the sampling clock.