Delay chain and method of operating same

A method of operating a delay chain, the method comprising:

• coupling delay stages in series as representing the delay chain,
• for each of the delay stages, the coupling the delay stages including:
• coupling a driver device between an input node and an output node of the delay stage;
• and
• coupling a capacitor digital-to-analog converter (CDAC) to the output node of the delay stage, wherein, for at least one of the delay stages, the corresponding CDAC being a separately adjustable (SA) type of CDAC (SA_CDAC) that is separately adjustable relative to the CDAC of at least another one of the delay stages,
• each of the at least one SA_CDAC being a one-dimensional array of separately controllable capacitance (SCC) cells (SCC_cells), the one-dimensional array including rows and a single column, and each of the rows including a corresponding single one the SCC_cells, and
• each of the SCC_cells being separately controllable to be coupled to the output node of the corresponding delay stage relative to other ones of the SCC_cells;
• adjusting at least one CDAC separately relative to at least another one of the CDACs;
• and
• selectively coupling none or some or all of the SCC_cells in the at least one SA_CDAC to the output node of the corresponding delay stage.

A delay chain comprising:

• delay stages coupled in series, each delay stage including:
• a driver device coupled between an input node and an output node of the delay stage;
• and
• a capacitor digital-to-analog converter (CDAC) coupled to the output node of the delay stage;
• at least one of the CDACs being a separately adjustable (SA) type of CDAC (SA_CDAC) that is separately adjustable relative to at least another one of the CDACs;
• the at least one SA_CDAC being a one-dimensional array of separately controllable capacitance (SCC) cells (SCC_cells),
• each SCC_cell being separately controllable to be coupled to the output node of the corresponding delay stage relative to other ones of the SCC_cells,
• the one-dimensional array including rows and a single column, and
• each row including a single SCC_cell;
• and
• a controller configured to adjust the at least one CDAC by selectively coupling none or some or all of the SCC_cells in the at least one SA_CDAC to the output node of the corresponding delay stage.