Method and device for implementing a matrix operation

A method for implementing a matrix operation using a plurality of memristors, a first memristor array including a first subset of the plurality of memristors and a second memristor array including a second subset of the plurality of memristors, the method comprising:

• determining a first digital result as a function of a first analog addition using the first memristor array;
• and
• determining a second digital result as a function of a second analog addition using the second memristor array;
• wherein:
• the determining of the first digital result and of the second digital result is performed by:
• applying a first voltage, which is an analog signal generated by a first digital-to-analog converter as a function of a digital signal defined by a first element of a matrix, at a first one of the plurality of memristors;
• and
• at least partially in a temporally overlapping manner with the application of the first voltage at the first memristor, applying a second voltage, which is an analog signal generated by a second digital-to-analog converter as a function of a digital signal defined by a second element of the matrix, at a second one of the plurality of memristors;
• and
• the first and second voltages differ by a factor which is defined:
• as a function of a resolution of the respective digital-to-analog converters;
• or
• as a function of a bit factor decomposition underlying the matrix operation.

A non-transitory machine-readable memory medium on which is stored a computer program for implementing a matrix operation, the computer program, when executed by a computer, causing the computer to perform the following steps:

• determining a first digital result as a function of a first analog addition using a first memristor array;
• and
• determining a second digital result as a function of a second analog addition using a second memristor array;
• wherein:
• a first voltage is applied at a first memristor of the first memristor array, the application of the first voltage at the first memristor being made selectively at a memristor level without global application of the first voltage to an entirety of the first memristor array;
• at least partially in a temporally overlapping manner with the application of the first voltage at the first memristor:
• a second voltage is applied, selectively at the memristor level, at a second memristor of the first memristor array;
• the first voltage is applied, selectively at the memristor level, at a third memristor of the second memristor array;
• and
• the second voltage or a third voltage is applied, selectively at the memristor level, at a fourth memristor of the second memristor array;
• a first total current is detected at a first output of the first memristor array, which characterizes a current flow through the first memristor and through the second memristor;
• a second total current is detected at a second output of the second memristor array, which characterizes a current flow through the third memristor and through the fourth memristor;
• and
• the first voltage and the second voltage differ by a factor which is defined as a function of a resolution of a plurality of digital-to-analog converters used for generating the first and second voltages or as a function of a bit factor decomposition underlying the matrix operation.

A device for implementing a matrix operation, comprising:

• a digital-to-analog converter arrangement consisting of one digital-to-analog converter or consisting of a plurality of digital-to-analog converters;
• a first memristor array;
• a second memristor array;
• a first analog-to-digital converter;
• and
• a second analog-to-digital converter;
• wherein:
• the device is configured to determine a first digital result as a function of a first analog addition using the first memristor array and the first analog-to-digital converter, and to determine a second digital result as a function of a second analog addition using the second memristor array and the second analog-to-digital converter;
• the digital-to-analog converter arrangement is configured to respond to digital signals, which are obtained for performance of the matrix operation, by:
• applying a first voltage at a first memristor of the first memristor array, the application of the first voltage at the first memristor being made selectively at a memristor level without global application of the first voltage to an entirety of the first memristor array;
• and
• at least partially in a temporally overlapping manner with the application of the first voltage at the first memristor:
• applying, selectively at the memristor level, a second voltage at a second memristor of the first memristor array;
• applying, selectively at the memristor level, the first voltage at a third memristor of the second memristor array;
• and
• applying, selectively at the memristor level, the second voltage or a third voltage at a fourth memristor of the second memristor array;
• the first analog-to-digital converter is configured to detect, and convert into the first digital result, a first total current at a first output of the first memristor array, which characterizes a current flow through the first memristor and through the second memristor;
• and
• the second analog-to-digital converter is configured to detect, and convert into the second digital result, a second total current at a second output of the second memristor array, which characterizes a current flow through the third memristor and through the fourth memristor;
• and
• the first voltage and the second voltage differ by a factor which is defined (a) as a function of a resolution of the one digital-to-analog converter or the plurality of digital-to-analog converters or (b) as a function of a bit factor decomposition underlying the matrix operation.

A device, comprising:

• a microprocessor;
• a switching unit including a plurality of electrical switches;
• and
• a memory including registers;
• wherein:
• the microprocessor is configured to operate the switches with a switching operation for selective application of voltages, the selective application activating a first device for implementing a matrix operation, the first device including:
• a first memristor array;
• a second memristor array;
• a first analog-to-digital converter;
• and
• a second analog-to-digital converter;
• the first device is configured to determine a first digital result as a function of a first analog addition using the first memristor array and the first analog-to-digital converter, and to determine a second digital result as a function of a second analog addition using the second memristor array and the second analog-to-digital converter;
• the microprocessor is configured to perform the switching operation of the switching unit to:
• apply a first voltage of the voltages at a first memristor of the first memristor array, the application of the first voltage at the first memristor being made selectively at a memristor level without global application of the first voltage to an entirety of the first memristor array;
• at least partially in a temporally overlapping manner with the application of the first voltage at the first memristor:
• apply, at the memristor level, a second voltage of the voltages selectively at a second memristor of the first memristor array;
• apply, at the memristor level, the first voltage selectively at a third memristor of the second memristor array;
• and
• apply, at the memristor level, the second voltage or a third voltage of the voltages selectively at a fourth memristor of the second memristor array;
• a first total current is detectable at a first output of the first memristor array, which characterizes a current flow through the first memristor and through the second memristor;
• a second total current is detectable at a second output of the second memristor array, which characterizes a current flow through the third memristor and through the fourth memristor;
• a result obtained from the first and second total currents is storable by the microprocessor in the registers;
• and
• the first voltage and the second voltage differ by a factor which is defined as a function of a resolution of a plurality of digital-to-analog converters used for generating the first and second voltages or as a function of a bit factor decomposition underlying the matrix operation.