Sixty gigahertz multiple input multiple output transceiver

A system-on-chip (SoC) device for a communication system, the SoC device comprising:

• a first communication interface configured to receive data in the communication system;
• a producer port linked with a consumer port through direct memory access (DMA), wherein data received by the first interface is assigned to the producer port;
• dual hardware media access controls (MACs) configured to consume the data assigned to the producer port;
• and
• at least one processor configured to supply the data to a wireless interface for transmission to another wireless communication device of the communication system at a frequency of at least sixty Gigahertz,
• wherein the wireless interface includes at least one beamforming chip configured to transmit wireless communication signals,
• wherein an aggregation layer of the SoC device is configured to synchronize the dual MACs and reassemble two independent MAC data streams into a single data stream,
• wherein the aggregation layer is configured to reorder out-of-order data frames using 802.11 protocol sequence numbers, committing only in-order frames to a next processing step and holding out-of-order data frames until they can be reordered or a timeout occurs, and
• wherein the at least one processor is configured to reduce a specified modulation rate in response to an out-of-order frame arrival rate increasing above a specified degradation threshold, and increase the specified modulation rate in response to the out-of-order frame arrival rate decreasing below the specified degradation threshold.