Impedance calibration for SERDES transmitter driver

An apparatus comprising:

• means for generating a first current that is representative of current flowing through a termination impedance of an output driver;
• means for generating a second current that is representative of current flowing through a replica driver comprising one or more replicas of a driver segment in the output driver;
• and
• a current comparator configured to compare the first current and the second current, wherein the means for generating the second current comprises:
• a first plurality of transistors powered by a first power rail;
• a second plurality of transistors powered by the first power rail;
• a replica driver stage coupled between the first power rail and ground through the first plurality of transistors, the replica driver stage comprising one or more replicas of a driver segment in the output driver;
• an error amplifier having a first input coupled to a reference voltage source, a second input coupled to a node through which the output of the first plurality of transistors is coupled to the replica driver stage, and an output coupled to a gate of each transistor in the first plurality of transistors and a gate of each transistor in the second plurality of transistors;
• a third plurality of transistors that is included in a current mirror and configured to receive a current from the second plurality of transistors;
• and
• at least one mirror transistor configured to provide an output of the current mirror to a second input of the current comparator.

A method for calibrating an output driver, comprising:

• generating a first current that is representative of current flowing through a termination impedance of an output driver;
• generating a second current that is representative of current flowing through a replica driver stage comprising one or more replicas of a driver stage in a driver segment in the output driver;
• and
• comparing the first current and the second current using a current comparator, wherein generating the second current comprises:
• controlling gate voltage of a first plurality of transistors configured to provide a reference current to the replica driver stage to maintain a predefined voltage across the replica driver stage,
• wherein the gates of the first plurality of transistors are coupled to gates of a second plurality of transistors that is configured to provide a scaled version of the reference current to a third plurality of transistors that is included in a current mirror, and wherein the second current is received from the current comparator.