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US 12,712,535 B2Granted
Integrated circuit and method of forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYueh Chiang, Shang-Hsuan Chiu, Ming-Xiang Lu, Kuang-Ching Chang
Life of this patent
Estimating the term…
Abstract
A flip-flop includes a first input circuit, a first NAND logic gate, a first stacked gate circuit, a first NOR logic gate, a first output circuit and a first set buffer circuit. The first input circuit is coupled to a first node. The first NAND logic gate is coupled between the first and second node. The first stacked gate circuit is coupled between the first and third node, and configured to generate a third signal responsive to the first signal. The first NOR logic gate is coupled between the third node and a fourth node. The first output circuit is coupled to the fourth node. The first set buffer circuit is coupled to the first NOR logic gate.
Claims20
A flip-flop comprising:
- a first input circuit coupled to a first node, and being configured to generate a first signal responsive to at least a first data signal, a first clock signal, or a second clock signal inverted from the first clock signal;
- a first NAND logic gate coupled between the first node and a second node, and being configured to generate a second signal responsive to the first signal and a first set signal;
- a first stacked gate circuit coupled between the first node and a third node, the first stacked gate circuit being configured to generate a third signal responsive to at least the first signal;
- a first NOR logic gate coupled between the third node and a fourth node, and being configured to generate a fourth signal responsive to the third signal and a second set signal inverted from the first set signal;
- a first output circuit coupled to the fourth node, and being configured to generate a first output signal responsive to the fourth signal;
- and
- a first set buffer circuit coupled to the first NOR logic gate, the first set buffer circuit being configured to generate the second set signal responsive to the first set signal.
4 more elements
A flip-flop comprising:
- a first input circuit coupled to a first node, and being configured to generate a first signal responsive to at least a first data signal, a first clock signal or a second clock signal inverted from the first clock signal;
- a first NAND logic gate coupled between the first node and a second node, and being configured to generate a second signal responsive to the first signal and a first set signal;
- a first stacked gate circuit coupled between the first node and a third node, the first stacked gate circuit being configured to generate a third signal responsive to at least the first signal;
- a first NOR logic gate coupled between the third node and a fourth node, and being configured to generate a fourth signal responsive to the third signal and a second set signal inverted from the first set signal;
- a first reverse stacked gate circuit coupled between the first node and the second node, the first reverse stacked gate circuit being configured to set the first signal responsive to the second signal;
- and
- a first set buffer circuit coupled to the first NOR logic gate, the first set buffer circuit being configured to generate the second set signal responsive to the first set signal.
4 more elements
A flip-flop comprising:
- a first input circuit coupled to a first node, and being configured to generate a first signal responsive to at least a first data signal, a first clock signal, or a second clock signal inverted from the first clock signal;
- a first NAND logic gate coupled between the first node and a second node, and being configured to generate a second signal responsive to the first signal and a first set signal;
- a first stacked gate circuit coupled between the first node and a third node, the first stacked gate circuit being configured to generate a third signal responsive to at least the first signal;
- a first NOR logic gate coupled between the third node and a fourth node, and being configured to generate a fourth signal responsive to the third signal and a second set signal inverted from the first set signal;
- a first reverse stacked gate circuit coupled between the first node and the second node, the first reverse stacked gate circuit being configured to set the first signal responsive to the second signal;
- a first output circuit coupled to the fourth node, and being configured to generate a first output signal responsive to the fourth signal;
- and
- a first set buffer circuit coupled to the first NOR logic gate, the first set buffer circuit being configured to generate the second set signal responsive to the first set signal.
5 more elements
Dependencies are inferred from the claim text.