Level shifter and memory device including the same
AssigneeSamsung Electronics Co., Ltd.
InventorJisoo Lee
Life of this patent
Estimating the term…
Abstract
A level shifter includes a first circuit that pulls down a first output node and a first intermediate node based on an input signal, and pulls down a second output node and a second intermediate node based on an inverted input signal of the input signal, and a second circuit that pulls up the second output node based on the first intermediate node when the first circuit pulls down the first output node to a supply voltage, and pulls up the first output node based on the second intermediate node to the supply voltage when the first circuit pulls down the second output node.
Claims15
A level shifter comprising:
- a first circuit configured to pull down a first output node and a first intermediate node based on an input signal, and pull down a second output node and a second intermediate node based on an inverted input signal of the input signal;
- and
- a second circuit configured to pull up the second output node to a supply voltage based on the first intermediate node when the first circuit pulls down the first output node, and pull up the first output node to the supply voltage based on the second intermediate node when the first circuit pulls down the second output node,
- wherein the second circuit comprises:
- a first transistor comprising a drain terminal connected to a first node, a source terminal connected to the second intermediate node, and a gate configured to receive a first bias signal,
- a second transistor comprising a drain terminal connected to a line configured to apply the supply voltage, a source terminal connected to the first output node, and a gate connected to the first node,
- a third transistor comprising a drain terminal connected to the first intermediate node, a source terminal connected to a second node, and a gate configured to receive the first bias signal, and
- a fourth transistor comprising a drain terminal connected to the line configured to apply the supply voltage, a source terminal connected to the second output node, and a gate connected to the second node.
A memory device comprising:
- a row address decoder including a level shifter configured to:
- generate an output signal by pulling up a voltage level of a first node to a first voltage level different from a voltage level of a first input signal by a pull-up current flowing through a first path, when receiving a first input signal;
- shut off the pull-up current by a first driving current flowing through a second path different from the first path, when receiving a second input signal which is an inverted signal of the first input signal;
- and
- pull down the voltage level of a first node to a second voltage level different from the first voltage level by a second driving current flowing through a third path, when receiving the second input signal and shutting off the pull-up current;
- and
- a memory cell array including a word line configured to receive the output signal, and a plurality of memory cells connected to the word line,
- wherein the first driving current and the second driving current are configured to minimize a current fighting between the pull-up current and a pull-down current.
Dependencies are inferred from the claim text.