Communication circuit with analog duty-cycle detection

A circuit comprising:

• an analog duty-cycle detector circuit including:
• off-time detection circuitry having a first terminal, a second terminal, a third terminal, and a fourth terminal, the off-time detection circuitry including a first transistor and a first capacitor, the first transistor having a first terminal, a second terminal, and a control terminal, the first capacitor having a first terminal and a second terminal, the first terminal of the first transistor coupled to the first terminal of the off-time detection circuitry, the second terminal of the first transistor coupled to the first terminal of the first capacitor;
• on-time detection circuitry having a first terminal, a second terminal, a third terminal, and a fourth terminal, the on-time detection circuitry including a second transistor and a second capacitor, the second transistor having a first terminal, a second terminal, and a control terminal, the second capacitor having a first terminal and a second terminal, the first terminal of the second transistor coupled to the first terminal of the on-time detection circuitry, the second terminal of the second transistor coupled to the first terminal of the second capacitor;
• compare circuitry having a first terminal, a second terminal, and a third terminal, the first terminal of the compare circuitry coupled to the third terminal of the off-time detection circuitry, and the second terminal of the compare circuitry coupled to the third terminal of the on-time detection circuitry, the compare circuitry configured to compare a charge across the first capacitor and a charge across the second capacitor;
• and
• a controller having a reset control terminal, the reset control terminal coupled to the fourth terminal of the off-time detection circuitry and to the fourth terminal of the on-time detection circuitry.